标题: | 一种低操作功率/高速静态随机存取记忆体(SRAM)之电流模式的读/写电路及其SRAM晶片实现之应用 A Current-Mode Read/Write Circuit for Low Operation Power/High Speed SRAM and Its Application in SRAM Chip Implementation |
作者: | 汪鼎豪 Ding-Hao Wang 吴庆源 Ching-Yuan Wu 电子研究所 |
关键字: | 电流模式放大器;电流模式写入方法;pulse word line;current sense amplifier;current write;supply voltage;chip optimize |
公开日期: | 1999 |
摘要: | 设计一个低功率且高效能的静态存取记忆体时,常常着重于减少工作时的功率及备用状态的直流电流与漏电流。为了减少读写操作时所消耗的功率,各种读写模式被提出,以减少功率及增加读写的速度。本论文提出一种低操作功率且高速的读写电路。当位元线的电压仅需少许的改变,这种新的读写电路便能顺利的读出与更新资料。在读取资料时,此一电路可以减少功率消耗并且快速的读出记忆细胞内的资料;资料由外写入时,可以减少位元线与资料之驱动器的功率消耗。将这种新的读写电路应用在记忆体晶片上,能呈现高效能及低功率的读写特性。除了新读写电路的应用外,在减少功率与加快工作速度的考量下,整个记忆体的架构与电路都必须最佳化。以32Kx8 SRAM 为例,记忆体可分成四个区块,使得工作功率的消耗减少为原来的四分之一;记忆细胞内的电晶体最佳化,可以得到较好的杂讯容忍度;控制位元线的电压,可以加快更新资料的速度;使用脉波字线的技术,可以减少在做位元线平衡时所消耗的功率,并增加记忆细胞对资料的稳定性。最后,在准确的时序控制与新读写电路的配合之下,完成低功率及高速的记忆体晶片设计。 High-performance and low-power SRAM design always focus on reducing dynamic power dissipation at the operating state and decreasing DC current and leakage current at the standby state. To reduce operation power without decreasing read/write speed, we propose some special read/write mechanism instead of conventional voltage mode read/write circuit. In this thesis, we discuss a new current mode read/write circuit for low-power and high-speed SRAM. The current-write mechanism can reduce bit-line swing when data write in, not only decreasing power consumption but also speeding up writing access time. A new current-mode sensing amplifier is proposed to sense the bit line signal even though the voltage swing of the bit line is small, and the non-floating design reduces noise produced during sensing in the standby mode. By using the circuit stated above, SRAM chip can be implemented. For 32Kx8 SRAM design, the SRAM memory array is divided into four blocks, only one of the four blocks is in operation and others are in standby mode, so the operating power for driving the word-line load is only one quarter of memory array. Using NAND gate for buffer to substitute inverter chain can avoid power loss when address changes or when chip is at disable state. A hierarchical decoder design is used for high-speed decoding and lower power dissipation. The pulsed word line is used to save power consumption when the bit line is equalized. Using the techniques described above, we can achieve low-power and high-performance SRAM. Chapter 2 Low Operation Power and High-Speed Read Circuit with Current-Mode Sense Amplifier 2.1 Voltage-Mode Signal Delay versus Current Mode Signal Delay 5 2.2 Positive Feedback Design for Speeding up the Access Time 7 2.3 Clamped Bit-Line Sense Amplifier ( CBLSA ) 10 2.4 Hybrid Sense Amplifier 13 2.5 A New Current-Mode Sense Amplifier 16 2.6 Simulation Results and Efficiency Comparisons 23 Chapter 3 Low Operation Power and High-Speed Write Method 3.1 Conventional Voltage Writing Mechanism 26 3.2 Current Writing with Equalization Transistor 27 3.3 A New Current Writing Mechanism 30 3.4 Efficiency Comparisons 33 Chapter 4 Application in SRAM Implementation 4.1 Low-Power SRAM Architecture and Internal Supply Voltage 35 4.1.1 Internal Supply Voltage and Whole Chip Architecture 35 4.1.2 Decoder Implementation 37 4.2 Cell Design and Layout Implementation 39 4.2.1 Cell Description & Layout Implementation 39 4.2.2 Simulation Results 41 4.3 Word Line and Buffer Implementation 42 4.3.1 Divided Word-Line Mechanism 42 4.3.2 Pulsed Word-Line Mechanism [12] 43 4.3.3 Simulation Results of Pulsed Word-Line Structure 45 4.3.4 Input Buffer and IO Buffer Implementation 46 4.4 Timing Control Circuit and Whole Chip Implementation 47 4.4.1 Address Transition Detection and Data Transition Detection 47 4.4.2 Simulation Results of ATD Circuit and DTD Circuit 49 4.5 Simulation Results of Whole Chip Layout and Post Layout 49 Chapter 5 Conclusions and Future Work |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT880428068 http://hdl.handle.net/11536/65707 |
显示于类别: | Thesis |