一種低操作功率╱高速靜態隨機存取記憶體（SRAM）之電流模式的讀╱寫電路及其SRAM晶片實現之應用

Abstract

設計一個低功率且高效能的靜態存取記憶體時，常常著重於減少工作時的功率及備用狀態的直流電流與漏電流。為了減少讀寫操作時所消耗的功率，各種讀寫模式被提出，以減少功率及增加讀寫的速度。本論文提出一種低操作功率且高速的讀寫電路。當位元線的電壓僅需少許的改變，這種新的讀寫電路便能順利的讀出與更新資料。在讀取資料時，此一電路可以減少功率消耗並且快速的讀出記憶細胞內的資料；資料由外寫入時，可以減少位元線與資料之驅動器的功率消耗。將這種新的讀寫電路應用在記憶體晶片上，能呈現高效能及低功率的讀寫特性。除了新讀寫電路的應用外，在減少功率與加快工作速度的考量下，整個記憶體的架構與電路都必須最佳化。以32Kx8 SRAM 為例，記憶體可分成四個區塊，使得工作功率的消耗減少為原來的四分之一；記憶細胞內的電晶體最佳化，可以得到較好的雜訊容忍度；控制位元線的電壓，可以加快更新資料的速度；使用脈波字線的技術，可以減少在做位元線平衡時所消耗的功率，並增加記憶細胞對資料的穩定性。最後，在準確的時序控制與新讀寫電路的配合之下，完成低功率及高速的記憶體晶片設計。

High-performance and low-power SRAM design always focus on reducing dynamic power dissipation at the operating state and decreasing DC current and leakage current at the standby state. To reduce operation power without decreasing read/write speed, we propose some special read/write mechanism instead of conventional voltage mode read/write circuit. In this thesis, we discuss a new current mode read/write circuit for low-power and high-speed SRAM. The current-write mechanism can reduce bit-line swing when data write in, not only decreasing power consumption but also speeding up writing access time. A new current-mode sensing amplifier is proposed to sense the bit line signal even though the voltage swing of the bit line is small, and the non-floating design reduces noise produced during sensing in the standby mode. By using the circuit stated above, SRAM chip can be implemented. For 32Kx8 SRAM design, the SRAM memory array is divided into four blocks, only one of the four blocks is in operation and others are in standby mode, so the operating power for driving the word-line load is only one quarter of memory array. Using NAND gate for buffer to substitute inverter chain can avoid power loss when address changes or when chip is at disable state. A hierarchical decoder design is used for high-speed decoding and lower power dissipation. The pulsed word line is used to save power consumption when the bit line is equalized. Using the techniques described above, we can achieve low-power and high-performance SRAM. Chapter 2 Low Operation Power and High-Speed Read Circuit with Current-Mode Sense Amplifier 2.1 Voltage-Mode Signal Delay versus Current Mode Signal Delay 5 2.2 Positive Feedback Design for Speeding up the Access Time 7 2.3 Clamped Bit-Line Sense Amplifier ( CBLSA ) 10 2.4 Hybrid Sense Amplifier 13 2.5 A New Current-Mode Sense Amplifier 16 2.6 Simulation Results and Efficiency Comparisons 23 Chapter 3 Low Operation Power and High-Speed Write Method 3.1 Conventional Voltage Writing Mechanism 26 3.2 Current Writing with Equalization Transistor 27 3.3 A New Current Writing Mechanism 30 3.4 Efficiency Comparisons 33 Chapter 4 Application in SRAM Implementation 4.1 Low-Power SRAM Architecture and Internal Supply Voltage 35 4.1.1 Internal Supply Voltage and Whole Chip Architecture 35 4.1.2 Decoder Implementation 37 4.2 Cell Design and Layout Implementation 39 4.2.1 Cell Description & Layout Implementation 39 4.2.2 Simulation Results 41 4.3 Word Line and Buffer Implementation 42 4.3.1 Divided Word-Line Mechanism 42 4.3.2 Pulsed Word-Line Mechanism [12] 43 4.3.3 Simulation Results of Pulsed Word-Line Structure 45 4.3.4 Input Buffer and IO Buffer Implementation 46 4.4 Timing Control Circuit and Whole Chip Implementation 47 4.4.1 Address Transition Detection and Data Transition Detection 47 4.4.2 Simulation Results of ATD Circuit and DTD Circuit 49 4.5 Simulation Results of Whole Chip Layout and Post Layout 49 Chapter 5 Conclusions and Future Work