銅/低介電常數材料導線嵌刻製程整合關鍵技術之研究

Abstract

當半導體元件的線寬縮至0.25微米以下，多層導線的訊號傳送延遲時間(即金屬導線電阻與雜散電容的乘積)成為元件高速操作的瓶頸。使用低介電常數材料取代傳統的二氧化矽作為層間絕緣膜，可以有效降低雜散電容，是解決訊號傳送延遲的一個有效方式。另外一個解決方式是以低阻質的銅導線取代目前的鋁導線。本論文研究一種新的絕緣膜沈積技術-溫差液相沈積氟氧化矽。研究的目的，是要解決多層導線的訊號傳送延遲的問題。 未來介電常數低於3的介電質將會取代現在正投入量產的氟氧化矽。通常這些低介電常數材料表面需要覆蓋一層無機介電質，以避免在製程過程中受到損害。與其他無機介電質如SiO2、SiON或SiN相比，溫差液相沈積氟氧化矽具有低介電常數、低應力的優點，因此我們嘗試將溫差液相沈積氟氧化矽技術應用在銅/低介電常數材料導線結構作為覆蓋層。另一方面，在眾多可能的介電質中，旋覆式有機介電質methyl silsesquioxane (MSQ)非常具有潛力，因為它具有低且可調的(tunable)介電常數值(1.9-2.8)與極佳的熱穩定性(>500℃)。MSQ具有類似二氧化矽的Si-O網狀結構(network)和大量的碳氫雜質(以Si-CH3鍵存在)。要將溫差液相沈積氟氧化矽技術應用在銅導線/MSQ嵌刻製程中，首要步驟就是MSQ活性離子蝕刻。因此我們研究以氟碳電漿蝕刻MSQ薄膜。實驗結果顯示與二氧化矽薄膜相比，MSQ的蝕刻率較低，主要是因為內含的碳氫雜質會降低(蝕刻時)表面吸附的反應物的氟碳比值(fluorine-to-carbon ratio)。也因為表面較低的氟碳比值，蝕刻進行後MSQ薄膜表面的穩態(steady-state)氟碳聚合物(fluorocarbon polymer)的厚度也大於二氧化矽薄膜表面的聚合物。此外兩者圖形蝕刻(pattern etching)的結果也不相同。以適合蝕刻二氧化矽之低氟碳比的電漿蝕刻MSQ後，發現其溝槽空間有一異常的突出形狀。我們提出了可能的機制解釋這個異常的蝕刻圖形。我們也發現要得到較好的蝕刻圖形，必須以較高氟碳比的電漿蝕刻。 因為含有大量的碳氫雜質，MSQ容易在蝕刻後去光阻的灰化(ashing)過程被嚴重劣化。我們發現MSQ在灰化後，不僅介電常數大幅上升至7以上。膜質變得非常疏鬆，漏電流也上升2個數量級以上。為改善這個問題，我們提出了一個新穎的側壁覆蓋(sidewall capping)製程。在MSQ溝槽結構經蝕刻成形後，先以乾式電漿與濕式蝕刻的方式去除側壁上的氟碳聚合物，再以選擇性液相沈積，僅在MSQ溝槽的側壁成長一層氟氧化矽作為覆蓋層，以保護MSQ在後續的灰化過程不會被劣化。霍式紅外線光譜(FTIR)與熱脫附質譜儀(TDS)的結果也證實經過側壁覆蓋之MSQ溝槽的確未被灰化過程劣化，而仍保有原來化學鍵結。顯然側壁覆蓋製程可以有效解決灰化所引起的膜質劣化的問題。 由本研究的結果證實了溫差液相沈積氟氧化矽技術在銅導線/低介電常數材料嵌刻製程上確實極具應用價值。

As device geometry is scaled down to deep submicron region, the resistance-capacitance (RC) delay of interconnection becomes a dominant part of the total delay for device switching. Conventional aluminum wires with a resistivity of 3.0 mW?cm and SiO2 intermetal dielectric (IMD) with a dielectric constant of 4.2 gradually become unacceptable. Copper (Cu) wire with a low resistivity of 1.8 mW?cm is required to reduce the resistance. On the other hand, a novel IMD with a low dielectric constant is also required to replace the conventional SiO2 for reducing the parasitic capacitance. In this thesis, temperature-difference-based liquid-phase deposition (TD-LPD) technology is developed to resolve the RC delay issue. In the near future, ultra-low-k (<3) dielectrics will be gradually employed to replace SiOF. These ultra-low-k dielectrics are generally less thermally and mechanically robust than conventional SiO2, and needs to be capped by thin layers of inorganic dielectrics such as SiOF, SiO2 or SiON. Among these inorganic dielectrics, TD-LPD SiOF as a capping layer is preferable due to its merits of low dielectric constant and low stress. On the other hand, among a variety of ultra-low-k dielectrics, organic SiO2-like methylsilsesquioxane (MSQ) is very promising due to low and tunable dielectric constant (1.9-2.8) and excellent thermal stability (>500℃). We thus attempt to apply the TD-LPD SiOF film as a capping layer on MSQ as an inter-Cu-metal dielectric. To be integrated with Cu using damascene process, the MSQ film must be first patterned into trenches to facilitate formation of Cu wires. However, there are primary two key issues in patterning MSQ. One issue is that the etching technology for MSQ has not been well developed. The other issue is that the MSQ can be easily degraded in the resist ashing step. Reactive ion etching of blanket MSQ film and MSQ trench are thus studied. The etch rate and the trench profile as a function of CHF3/CF4 flow rate ratio for MSQ are investigated and compared with those of SiO2. The etch rate for MSQ is slower than that of SiO2. For CF4/CHF3 flow rate ratio of 0.5, the etching profile is peculiar with hillock in the trench space. The peculiar profile is not observed for SiO2 trench. For a high CF4/CHF3 flow rate ratio of 2, the etching profile is normal. This result reveals that CF4/CHF3 flow rate ratio of 2 is a suitable condition for MSQ trench etching. The mechanism for the slower etch rate and the peculiar etching profile for MSQ has also been clarified. Ashing-induced degradation on MSQ is also a critical issue for Cu/MSQ integration. To resolve the issue, we has proposed and demonstrated a novel sidewall capping technology for preparing degradation-free MSQ trenches. Prior to resist ashing, a layer of SiOF film is selectively deposited onto the sidewalls of MSQ trenches using TD-LPD. This novel sidewall capping technology using TD-LPD has been verified effective in resolving the ashing-induced degradation problem. Results in this thesis demonstrate that TD-LPD is indeed a highly promising technology for application in damascene processes of Cu/low-k dielectric interconnection. Chinese Abstract i English Abstract iii Acknowledgements v Contents vi Table Captures vii Figure Captures ix Chapter 1 Introduction and Thesis Organization 1.1 Background and Motivations 1 1.2 Thesis Organization 4 Chapter2 Process-Induced Damage on SiOF Damascene Trench and It's Effective Solution for Thermally Reliable Cu/SiOF Interconnection 2.1 Introduction 8 2.2 Experimental Procedures 9 2.3 Results and Discussions 11 2.4 Summary 13 Chapter 3 Reactive Ion Etching of Methylsilsesquioxane using CF4/CHF3 Feedgas Chemistries 3.1 Introduction 26 3.2 Experimental 26 3.3 Results and Discussion 28 3.4 Summary 31 Chapter4 Innovative Sidewall Capping Technology for Degradation-Free Damascene Trenches of Low-K Methylsilsesquioxane 4.1 Introduction 42 4.2 Experimental 43 4.2.1 Procedures for Investigation of Ashing-Induced Degradation 43 4.2.2 MSQ Trenches with Sidewall Capping Technology 43 4.2.3 Procedures for Investigation of Step Coverage 45 4.2.4 Investigating Effects of O2-plasma Cleaning and Wet Cleaning on MSQ 45 4.2.5 Evaluating Effectiveness of Sidewall Capping 45 4.2.6 Cu sputtering and CMP Cu 45 4.2.7 Replacing the passivation layer SiNx with Teos 46 4.2.8 Resistance Measurement 46 4.3 Ashing-Induced Degradation 46 4.4 SEM Investigation of Degradation-Free MSQ Trenches 47 4.5 Step Coverage of LPD Film 47 4.6 Effect of Sidewall Cleaning on MSQ 48 4.7 Effectiveness of Sidewall Capping 49 4.8 Discussion on Peeling effect during CMP process 50 4.9 Successful integrated Cu/MSQ damascence interconnection 50 4.10 Discussion on Multilevel Integration with Sidewall Capping Technology 52 4.11 Summary 52 Chapter 5 Conclusions and Future Works 5.1 Conclusions 72 5.2 Suggestions for Future Work 74 5.2.1 Modification of Present Sidewall Capping Technology 74 5.2.2 Integration of Cu/MSQ with Modified Sidewall Capping Technology 75 Table Capture Table2-1 The process parameters for two-step CMP Table2-2 Summary of plasma annealing conditions Figure Captions Fig.2-1 the process flow of the LPD FSG dielectrics for single Cu damascence structure. Fig.2-2 the structure for single Cu interconnect. Fig2-3 the layout and cross section of our Cu damascence structure. Fig2-4 the method for resistance test Fig.2-5 the SEM of integration for Cu and LPD FSG dielectrics Fig.2-6 the thermal resistance of single Cu interconnection : top one has N2O plasma annealing after RIE dielectrics; bottom one doesn't have N2O plasma annealing after RIE dielectrics. Fig.2-7(a) the process flow is designed for proving the exact site of trench outgassing source. Fig.2.7(b) the sheet resistance of the blanket dielectric after RIE process. Fig.2-8(a) SIMs spectra of N, F, and Si in as deposited LPD FSG Fig.2-8(b) SIMs spectra of N, F, and Si in LPD FSG after N2O plasma annealing Fig.2-9 Dielectric constant of LPD FSG with (a) as deposited, (b) 15min N2O plasma annealing, (c) 30min N2O plasma annealing. Fig. 3-1 The etch rate as a function of CF4/CHF3 flow rate ratio for MSQ and SiO2. Fig. 3-2 (a) XPS spectra of C 1s for the MSQ and SiO2 films partially etched at a CF4/CHF3 flow rate of 0.5, (b) the polymer thickness as a function of CF4/CHF3 flow rate ratio for the both films. Fig. 3-3 SEM cross-sectional pictures of MSQ trench etched at CF4/CHF3=0.5 for the pitch size being (a) 1.2 mm, (b) 1.6 mm, (c) 2.0 mm, and (d) 4.0 mm. Fig. 3-4 SEM cross-sectional pictures of MSQ trench etched at CF4/CHF3=1 for the pitch size being (a) 1.2 mm, (b) 1.6 mm, (c) 2.0 mm, and (d) 4.0 mm. Fig. 3-5 SEM cross-sectional pictures of MSQ trench etched at CF4/CHF3=2 for the pitch size being (a) 1.2 mm, (b) 1.6 mm, (c) 2.0 mm, and (d) 4.0 mm. Fig. 3-6 SEM cross-sectional pictures of SiO2 trench etched at CF4/CHF3=0.5 for the pitch size being (a) 2.0 mm, and (b) 4.0 mm. Fig. 3-7 Schematic diagram of deflected ions and reflected ions into the trench space. Fig. 4-1 Schematic demonstration of ashing-induced degradation on the MSQ trench sidewall in the conventional patterning and resist-stripping process. Fig. 4-2 Cross-sectional SEM images for MSQ trenches after (a) trench patterning, (b) sidewall cleaning, (c) sidewall capping and (c) resist stripping. Fig. 4-3 FTIR spectra for MSQ film before and after ashing. Fig. 4-4 (a) dielectric constant, (b) leakage current density, and (c) thickness for MSQ film before and after ashing. Fig. 4-5 Cross-sectional SEM images for MSQ trenches after (a) trench patterning, (b) sidewall cleaning, (c) sidewall capping and (c) resist stripping. Fig.4-6 SEM cross-sectional views of LPD SiOF deposited on a TEOS oxide trench. Fig. 4-7 shows the MSQ thickness as a function of O2-plasma cleaning time. Fig. 4-8 MSQ film thickness as a function of wet cleaning time with O2-plasma cleaning time as a parameter. Fig. 4-9 SEM cross-sectional picture of MSQ trench without wet cleaning after sidewall capping. Fig. 4-10 FTIR spectra of MSQ film with capping before/after ashing. Fig. 4-11 TDS spectra of H2O for the MSQ trenches with/without sidewall capping after ashing.