積體電路晶片在封裝前利用鎢探針量測系統及相關製程技術

Abstract

隨著電子應用產品體積越來越縮小的趨勢，先進晶圓階段封裝技術已被發展出來。這些尖端封裝技術比起傳統的封裝技術花費更多的封裝成本。 為了節省封裝成本，晶圓階段測試將成為下世代的競爭力關鍵。在封裝前事先知道哪一個晶片是良好的變成一件非常重要的事情。許多人已經提出數種元件及方法來做封裝前量測。 這裡我們提出一個新的元件結構來從事晶粒尺寸般大小的封裝前量測。相關的流程與製作技術已被開發出來，並做詳細的探討與研究。最後並附上一些各方先進已發展的元件結構以供參考。

As the electronic application products are tending to the more and more small, modern wafer level packaging has to be developed. This technology cost much more than those of the traditional packaging methods. For saving the packaging cost, wafer level testing is the next generation main issue. Knowing which die is good becomes important before packaging. Many people have mentioned several kinds devices to testing. Here we give a new device structure to testing in the die size. Related process and fabrication technology have studied detail. And some others testing devices presented are shown at last. Chinese abstract English abstract Acknowledgment Contents Chapter 1 Introduction……………………………………………………1 1-1 Background and trend 1-2 Modern wafer level testing Chapter 2 Device Structure Fabrication and Measuring Principle………4 2-1 Device fabrication 2-2 Process flow 2-3 Measuring principle Chapter 3 Process Technology…………………………………………9 3-1 Silicon dioxide deposition 3-2 RIE of silicon dioxide and tungsten 3-2.1 Issue 1. Fluorine-to-carbon ratio theory for oxide etching 3-2.2 Issue 2. The ion bombardment assisted etching 3-2.3 Issue 3. Reactive ion etch (RIE) principle 3-2.4 Etching of the tungsten film 3-3 Tungsten deposition Chapter 4 Experimental Results and Discussion……………………13 4-1 Silicon dioxide deposition 4-2 Silicon dioxide etching 4-3 The tungsten pillars and probes deposition 4-4 Remove the selective loss 4-5 Blanket tungsten deposition on silicon dioxide surface 4-6 CMP and HF acid remove the silicon dioxide Chapter 5 Comparison with Other Present Probe Cards……………16 Chapter 6 Conclusion…………………………………………………17 Chapter 7 The Future Work……………………………………………18 Reference Table Figure Captions