標題: 利用超高真空化學氣相沉積系統製造複晶矽電晶體之研究
Study of polycrystalline Silicon thin film transistors fabricated
作者: 顏承正
Cheng-Zheng Yen
張俊彥
Chun-Yen Chang
電子研究所
關鍵字: 薄膜電晶體;超高真空化學氣相沉積系統;薄膜電晶體之可靠度分析;thin film transistors;UHVCVD;Reliability of passivated poly-Si TFTs
公開日期: 1999
摘要: 以超高真空化學氣相沈積系統(UHV/CVD)所成長的複晶矽薄膜電晶體,其臨界電壓與載子遷移率在同一片晶片上的均勻度都優於以低壓化學氣相沈積系統(LPCVD)所成長的複晶矽薄膜電晶體─超高真空化學氣相沈積系統製造的複晶矽薄膜電晶體其臨界電壓的標準差為±0.16V、載子遷移率標準差為±10%;然而以低壓化學氣相沈積非晶矽再結晶成複晶矽薄膜電晶體的臨界電壓標準差為±0.23V、載子遷移率標準差為±21%。 在本論文中,我們利用NH3來作為元件做鈍化處理的氣體,經氣體鈍化處理後的元件電性均有明顯改善。如載子遷移率上升、臨界電壓下降、次臨界波動變小以及缺陷密度下降等。由於SiH4氣體是直接沈積複晶矽薄膜,其表面較粗糙,相較於Si2H6氣體因沉積速率快,先形成非晶矽再結成複晶矽之薄膜電晶體,前者的載子遷移率較低─經鈍化處理後為7.13cm2/V-s(n-型電晶體);而後者載子遷移率較高─經鈍化處理後為29.8cm2/V-s(n-型電晶體)。 在本論文中發現經過鈍化處理後的元件可靠度較未做鈍化處理的元件好;加大電壓stress後,發現經過鈍化處理的元件特性有較小的變動值─臨界電壓變大、次臨界波動變大、漏電流上升等。
The ultra high vacuum chemical vapor deposition (UHV/CVD) system can deposite poly-Si film without any laser or furnace annealing. The deposition pressure is superior to that deposited by low pressure chemical vapor deposition (LPCVD) system. The threshold voltage and mobility deviation for UHV/CVD are and 100mtorr~120mtorr for LPCVD system. In this thesis, NH3 was used to passivate the devices. It has obvious improvement on device performance after plasma passivation, i.e. the mobility increases、threshold voltage decreases、subthreshold swing decreases and trap state density decreases. In this thesis , we fabricated TFT devices with Si2H6 and SiH4 gas source by UHVCVD.However, due to the deposition in polycrystalline phase for SiH4 gas source, the film surface is rough and results in low field effect mobility (7.13cm2/V-s, after plasma passivation, n-type device) compared to that (29.8cm2/V-s, after plasma passivation, n-type device) obtained using disilane (Si2H6) in amorphous phase first than recrystallized through high temperature process. .After passivation, the devices show a better stress endurance compared to unpassivated devices. 1.1 Overview of polycrystalline silicon thin film transistor technology 1 1.3 Motivation 3 1.4 Organization 3 Reference 5 Chapter 2 Characteristics of poly-Si films deposited by UHV/CVD 7 2.1 Introduction 7 2.2 Defects in poly-Si films 8 2.3 The poly-Si films and deposition environment 9 2.2.1 Films deposited by UHV/CVD and LPCVD 9 2.2.2 Grain size 9 2.2.3 Description of the UHV/CVD system 10 2.3 Methods of Device parameter extraction 10 2.4 Extraction of the trap state density from the TFT characteristics 10 2.4.1 Determination of the field effect mobility Measurement of the trap state density in poly-Si films 11 2.4.2 Determination of the threshold voltage 11 2.4.3 Determination of trap state density in polycrystalline silicon by field effect conductance 11 2.4.3-1 Determination of the trap state density,Nt, from the ln[Ids/(Vg-VFB)] versus (Vg-VFB)-2 characteristics 13 2.4.3-2 Determination of the density of state Reference 16 Chapter 3 Fabrication of poly-Si TFTs using UHV/CVD deposited poly-Si films 18 3.1 Introduction to poly-Si films deposited by LPCVD and UHV/CVD 18 3.1.1 UHV/CVD poly-Si films 19 3.1.2 Device fabrication 19 3.1.3. Poly-Si films deposited by UHV/CVD 19 3.2 Plasma treatment condition 20 3.3 Results and discussion 21 3.3.1 Without plasma treatment 21 3.3.2 With plasma treatment 22 Reference 26 Chapter 4 Reliability of passivated and unpassivated poly-Si TFTs 28 4.1 Introduction 28 4.2 Stress condition 28 4.3 Results and discussion 28 4.4 Temperature Effect 31 4.5 Activation energy 31 Chapter 5 Conclusions 38
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT880428096
http://hdl.handle.net/11536/65738
顯示於類別:畢業論文