寬頻分碼多重進接空–時耙狀接收器之DSP實現及實驗研究

Abstract

近年來根據寬頻分碼多重進接技術，以軟體無線電架構來實現第三代無線行動通訊系統，已成為一個極受囑目的話題。在本論文中，吾人首先介紹一種軟體無線電平台的概念，稱為分層架構。接著，吾人介紹兩種主要的軟體無線電處理單元—可程式邏輯閘陣列和數位信號處理器。再者，在寬頻分碼多重進接系統下，吾人發展了一套空-時耙狀接收器以及空-時多階平行干擾消除器演算法，並根據TMS320C6201數位信號處理器應用板來模擬及實現其功能。由結果顯示，在多重進接干擾的環境下，空-時多階平行干擾消除器之效能明顯優於空-時耙狀接收器。此外，吾人亦提出空-時碼擷取演算法來估計時序，並在數位信號處理器應用板模擬及實現其功能。由結果證實，在強干擾環境下，空-時碼擷取演算法可以有效的提昇碼擷取的效能。

Recently, the use of software-defined radio (SDR) technology to implement the third-generation mobile communication systems, based on wideband code division multiple access (W-CDMA), has become a topic of great interest. In this thesis, the concept of layered architecture, which is the platform for the SDR, is first introduced. The properties of two major function units of SDR, i.e., FPGA's and DSP's, are then discussed. Third, the space-time RAKE (S-T RAKE) receiver and space-time multistage parallel interference canceller (S-T MPIC) for W-CDMA systems are developed, simulated and realized on a DSP applications board (TMS320C6201 based). From the results, we demonstrate that the S-T RAKE receiver equipped with S-T MPIC performs reliably in the presence of strong multiple access interference (MAI). In addition, code acquisition is incorporated to obtain the initial timing for the receiver. With the antenna array employed, an S-T code acquisition scheme results that can effectively combat strong traffic interference during the acquisition period of the signal. The proposed receiver, including S-T code acquisition, S-T RAKE receiver and S-T MPIC, is realized on the DSP board, and simulated data are used to confirm the effectiveness of the realization.