高介電常數介電層在金氧半元件及動態隨機存取記憶體上之特性研究

Abstract

隨著動態隨機存取記憶體(DRAM)科技之研究進入21世紀，元件尺寸不斷的微縮是其持續發展的動力。然而經由閘極介電層與汲極－基板接面穿隧而增加的漏電流是DRAM電晶體微縮所必須考慮的重要問題。為了滿足低待機電源之應用，利用高介電常數材料(high-κ)來取代二氧化矽是不可或缺的趨勢。本篇論文主要研究課題為高介電常數材料的特性，諸如崩潰電場、電荷捕獲以及溫度相關之可靠度問題，以期將高介電常數材料應用在閘極介電層與DRAM上。 本論文首先利用尖端放電電荷非接觸式半導體氧化層量測方法研究臭氧氣體沉積後退火溫度對於氧化鉭(Ta2O5)薄膜之影響。研究結果發現介電層厚度隨著退火溫度升高而增加，推測是由於界面層之成長所造成。電容之平帶電壓位移在經過臭氧氣體沉積後退火後由正位移轉為負方向之位移，是因為臭氧氣體沉積後退火會造成薄膜內被捕獲電子減少或者是電洞捕捉量增加。軟崩潰電場的增加以及均勻性的劣化主要是由於界面氧化層成長不均所導致。此外，高溫臭氧氣體沉積後退火能夠填補矽基板與氧化鉭薄膜界面之懸鍵進而降低界面缺陷密度。 其次，我們研究一種以臭氧水在室溫成長的薄氧化層基本特性。實驗結果發現臭氧水氧化層之成長速率與去離子水中臭氧濃度成正比。同時其具有自我限制的飽和成長特性可以改善經過爐管或是快速高溫氧化成長薄膜之厚度不均。臭氧水氧化層亦可以用來改善矽表面粗糙度達41%，很適合當作閘極介電層之前的界面處理來降低閘極的漏電流。其次，比較不同界面處理對於二氧化鉿(HfO2)閘極介電層電容特性之影響。結果顯示，經過臭氧水氧化層界面處理的元件具有較低的漏電流，可忽略的磁滯效應以及良好的介電可靠度，因此為改善高介電常數材料與矽基板界面特性之絕佳候選。 最後分別以捕獲效率、電導峰值位移以及缺陷產生率來探討不同界面處理對於二氧化鉿閘極介電層電荷捕獲特性的影響。臭氧水氧化層界面處理在經過600oC沉積後退火之後形成較佳的界面，因此相較於氨氣及快速高溫氧化前處理擁有最低的捕獲效率，界面缺陷劣化及缺陷產生率。然而，在未經過600oC沉積後退火處理之前，臭氧水氧化層由於低成長溫度所導致之不完全氧化以及較粗糙的界面，因此特性較差。此外，亦研究了二氧化鉿閘極介電層之漏電流傳輸機制，實驗顯示在有效電場小於3.5 MV/cm時，其相對應之漏電流傳輸機制為蕭基特發射主導，當電場界於3.5~6 MV/cm時，則是由Fowler-Nordheim穿隧所主導。

As DRAM enters the 21st century, the course of DRAM technology development continues to be driven by the need for smaller cell sizes. One major problem which must be considered in scaling of the DRAM transistor is increased leakage due to tunneling currents in the gate insulator and in the drain–body junction. It stresses the urgent need for high dielectric constant (κ) gate dielectrics for low stand-by power application. In this thesis, the dielectric properties of high-κ dielectrics, some reliability issues such as breakdown field, charge trapping and temperature-dependence behaviors were extensively studied for both gate dielectric and DRAM applications. The first objective of this thesis is the effects of O3 post deposition annealing temperature on the properties of Ta2O5 which were investigated by COCOS (Corona Oxide Characterization of Semiconductor) non-contact metrology. It was found that the dielectric thickness was increased as raising annealing temperature, which could be ascribed to the thick interfacial layer (IL) growth. Moreover, the flat band voltage shift changed from positive to negative due to the electron traps elimination and partially hole traps generation in the film. Non-uniform interfacial layer oxidation after O3 annealing was supposed to cause the increasing of the field strength and break the the soft breakdown distribution. It had been supposed that high temperature ozone annealing could compensate the dangling bond at the interface of Si/Ta2O5 proceed to minimize the interface trap density and improve the uniformity. Secondly, the basic properties of the ozone oxide were studied. The growth rate of ozone oxide was increased as raising the ozone quantity contained in DI water. A saturated oxidation was observed in the growth curves and the resultant self-limiting property could improve the thickness uniformity after furnace or/and rapid thermal oxidation. Ozone oxide could improve Si surface roughness by 41%, which was beneficial to suppress the leakage current density of the stacked gate dielectric. Then the influences of surface treatment prior to HfO2 gate dielectric deposition were investigated. As a result, sample with Ozone treatment revealed small leakage current, negligible hysteresis and excellent dielectric reliability, which was considered to be one of the most potential alternative to improve the interface properties between high-κ dielectrics and silicon surface. Finally, the surface treatment effects on the charge trapping characteristics the HfO2 gate dielectric were researched in terms of trapping efficiency, conductance peak shift, and SILC defect generation. Ozone oxide performed the lowest trapping efficiency, Dit degradation and defect generation rate after 600oC PDA than NH3 or RTO treatment partially due to the better interface properties. However, Ozone-samples without PDA expressed poor results, which might be caused by the incomplete oxidation and rougher interface owing to the low growth temperature. The current transport mechanism was also investigated. When Eeff<3.5 MV/cm, the corresponding current transport mechanism was Schottky emission under gate injection conditions. F-N tunneling dominated the conduction mechanism during 6>Eeff>3.5 MV/cm.