蕭基位障對奈米碳管電晶體與薄膜電晶體之影響

Abstract

自從奈米碳管於1998年被首次製作成奈米碳管電晶體之後，許多相關的研究便如火如荼的進行著。而許多奈米碳管電晶體的相關性質如雙極性電流特性等等也一一被發現。截至今日為止，蕭基位障模型是最普遍被人們所接受用來解釋奈米碳管電晶體之雙極性電流特性之模型。然而，卻只有一些直接證據可以證明奈米碳管電晶體是蕭基位障的元件。 在本論文中，我們提出了一種具有副閘極結構的元件結構，並且利用ISE TCAD元件模擬程式來模擬在不同副閘極電壓下的蕭基位障元件之電流特性。從模擬的結果中，我們發現因為蕭基位障會受到閘極電壓壓縮或是增厚，蕭基位障元件之ID-VG電流特性會出現雙極性的電流特性。而ID-VD特性則會因為汲極端的蕭基位障在不同的閘極電壓下，會受到汲極電壓的增加而降低位障高度，或是簡少位障厚度始得電流的變化出現完全不同的趨勢。 而當我們在副閘極施加正電壓時，也可以壓抑導帶的蕭基位障，並且增厚價帶的蕭基位障，因而使得電子的導通電流增加，並且減少電洞的導通電流，反之亦然。 實際的電性量測中發現蕭基位障薄膜電晶體與奈米碳管電晶體都可以量測到與模擬結果有相同趨勢的電流特性，而副閘極也可以影響其電流特性。然而奈米碳管電晶體因為其細微的準一維結構，使得其電流特性受到負閘極電壓的影響比起薄膜電晶體要小的多。 最後，我們將溫度模型引入模擬程式中來探討溫度對於蕭基位障薄膜電晶體與奈米碳管電晶體之作用。實際的量測結果中發現奈米碳管電晶體在不同溫度下的電流特性與模擬結果相符，但是蕭基位障薄膜電晶體會受到通道中的晶界所影響而出現與模擬結果相當大的差距。總而言之，本論文提出了數個直接證據說明奈米碳管電晶體可以視為一個單晶通道的蕭基位障元件。

Since the carbon nanotube field-effect transistor (CNTFETs) were proposed in 1998, lots of researches have been performed and many interesting properties have been reported, for example ambipolar behavior. Until now, Schottky barrier model (SB model) is the most accepted model to explain the ambipoar I-V behavior of CNTFETs. However, there are still little direct evidences to prove that the CNTFETs are Schottky barrier devices. In this work, we proposed a novel device structure with source/drain sub-gates and used ISE TCAD simulation program to reveal the behavior of the Schottky barrier devices with various sub-gate biases. From the simulation results, we found that due to the thickness of Schottky barrier would be thickened or be suppressed by the gate bias, the ID-VG behavior of SB devices shows ambipolar characteristic. Besides that, as a result of that the Schottky barrier at drain side is lowered or thinned at different gate bias, the ID-VD behavior shows completely different trend as the drain voltage increases. When we apply positive voltage at sub-gates, the Schottky barrier at conduction band will be suppressed and that at valance band will be thickened. Therefore, the electron current will increase and the hole current will decreases and vice versa. Electrical measurement shows that the CNTFETs and TFTs exhibit the same I-V characteristics trend with the simulation results and that the sub-gates could affect the characteristics of both CNTFETs and SBTFTs. However, due to the tiny one-dimensional geometry of CNT, the sub-gates have much less effect on CNTFETs. Finally, we included temperature model into the simulation program to investigate the temperature effect of SBTFTs and CNTFETs. The measured temperature effect of CNTFETs shows quite good agreement with the simulation results. However, as a result of grain boundary in actual SBTFTs channel, the measured results are quite different from the simulattion results. Conclusively, this work provides several direct evidences to support that the CNTFETs could be treated as SB devices with single crystalline channel.