後沉積之一氧化二氮氣體電漿處理對二氧化鉿堆疊式閘極金氧半場效電晶體電性之影響

Abstract

在元件尺寸快速微縮的需求下，傳統二氧化矽(SiO2)閘極介電層微縮到2奈米左右時，其量子穿隧效應引致漏電流已大到無法忍受。為解決此問題，用高介電材質諸如二氧化鉿(HfO2)，以取代傳統二氧化矽，乃勢在必行。然而，高介電係數之閘極介電層仍有許多待解問題，諸如，大量界面缺陷(interface state densities)，大量本體缺陷(Bulk traps)等。本論文中，我們嘗試使用一氧化二氮電漿氮化處理，以改善二氧化鉿閘極介電層的品質。 實驗中，我們發現一氧化二氮電漿氮化處理後，可以得到諸如較低閘極漏電流、較高電導頂峰值(Gm peak value)、較佳次臨界擺幅(substhreshold swing)、較低界面缺陷、和較低二氧化鉿本體缺陷等優點。在二氧化鉿閘極介電層中，電流傳導機制主要是Frenkel-Poole；經過氮化處理後，電子缺陷的能階變深，靠近閘極之傳導帶。且經氮化處理後，原本呈現捕捉電洞之行為，會轉變成捕捉電子。我們也發現，在固定電壓應力(CVS)、及負偏壓-溫度應力(NBTI)的可靠性測試中，電晶體之退化，乃緣於本體中之捕捉行為，而非由界面缺陷的增加。在動態應力(dynamic stress)可靠性測試下，我們發現，關閉時間(off-time)時釋放電洞之行為，及因開啟時間(on-time)太短，而來不及捕捉電洞，二者均須加以考量，方能解釋動態應力下臨界電壓漂移之行為。透過載子分離(carrier separation)量測，我們得以釐清，崩潰究竟是發生於二氧化鉿本體或是界面層。

With aggressive device scaling, shrinking the conventional thin silicon dioxide gate dielectric to the range of 2nm has caused an unbearable direct tunneling leakage current. To solve the problem, it is necessary to replace SiO2 by some high-k dielectric materials such as HfO2. However, there are many outstanding issues in high-k materials, such as high interface state densities, large amounts of bulk traps, etc. In this thesis, we try to use post-deposition N2O plasma nitridation to improve the HfO2 film quality. We found that N2O plasma nitridation brings about many advantages such as reduced gate leakage current, increased Gm peak value, better subthreshold swing, reduced interface states and bulk traps in the HfO2. The dominant current transport mechanism in HfO2 gate dielectric is of the Frenkel-Poole type, and the electron traps are located at a deeper energy position after N2O plasma nitridation. Also, the preponderant trapping behaviors become electron-trapping dominant, rather than hole-trapping dominant, after N2O plasma nitridation. Under the constant voltage stress (CVS) and negative bias temperature instability (NBTI), we found that bulk traps in HfO2, rather than interface state densities, are responsible for the transistor degradation. Under dynamic stress, both the off-time de-trapping and the lack of hole trapping due to short on-time are required to explain the behavior of threshold voltage degradation. Finally, through the help of carrier separation experiments, we have clarified whether the breakdown originates in the bulk or the interfacial layer.