氮化處理與氟摻雜對二氧化鉿堆疊式閘極介電層金氧半場效電晶體其電性特性與可靠性影響

Abstract

隨著CMOS技術急速的微縮到奈米技術點，傳統閘極介電層二氧化矽層將達到其物理與電性限制。主要的問題是的量子效應引發無法接受的大量的载子直接穿隧電流(Direct Tunneling Current)穿隧超薄二氧化矽層。為了可以有效的抑制此漏電流，高介電常數的閘極介電層材料會被使用來取代傳統的二氧化矽層而可以維持在相同的等效電性氧化層厚度(EOT)下增加實際介電層膜的厚度。在本論文中，我們對於具有二氧化鉿堆積式閘極介電層之金氧半元件與電晶體，研究不同氮化處理，如沉積前的不同氣體電漿處理、沉積後的N2O氣體電漿處理、後沉積低溫氨氣處理及氟併入到閘極介電層，對二氧化鉿堆積式閘極介電層其電性特性(如電荷捕捉)及固定偏壓電應力(constant voltage stress)、負偏壓不穩定(negative bias-temperature instability，NBTI)，AC電性應力(AC stress)..等可靠性議題。此外，我們也針對目前文獻很少發表有關於高介電層材料，其電漿損害效應做了深入探討，及其對於NBTI效應之影響和氟對於漿損害效應的改善影響。我們也對於目前高介電層材料的另一大問題，由於快速電荷捕捉所引起的電壓不穩定(Threshold voltage instability)，架設了可以對這些快速缺陷(Fast Transient Charge Trap, FTCT)作探討的單一脈波Id&Vg量測(Single-Pulsed Id&Vg)。 首先，我們探討了我們利用氨氣及一氧化二氮高密度電漿來處理矽基板表面，形成一層薄的含氮的介面層，及與ㄧ般傳統的二氧化矽介面層或是直接沉積 HfO2薄膜在矽基板上的閘極介電層，他們在電性上和可靠度上的差異，結果顯示經過高密度電漿處理過後的介面層電性較差，且漏電流仍然未達到我們要的標準，必須經由傳統的快速升溫回火來修補這些損害，所以修補後呈現出較小的漏電流、較小的磁滯、較小的頻率分散、較大的崩潰電壓。而就可靠度來說，經由氨氣電漿處理的試片會有最大的崩潰時間、崩潰電荷，以及最好的特性存活時間，所以用氨氣來作為表面處理的氣體是很好的選擇！我們發現對於由氮化鈦作為電極的電容，在二氧化鉿薄膜裡面主要的捕捉電荷機制是電洞捕捉而不是電子捕捉。而這種行為可以用捕獲面積模型來適當敘述。特別的是，平帶電壓平移是由於陷阱填補而不是陷阱產生.而電洞捕捉為主要機制可以歸因於電洞由基板注入的機率遠大於電子由閘極注入的機率而這是因為氮化鈦電極的功函數造成電洞具有較短的穿透路徑。 其次，我們提出一個改善二氧化鉿電性特性的後沉積低溫氨氣處理方法。於二氧化鉿介電層沉積後，但於後沉積退火前，使用低溫 (~400 ℃) 氨氣對二氧化鉿介電層做氮化處理，我們發現並有低溫氨氣處理的試片呈現出較好C-V特性、較小的頻率分散、較低的漏電流、崩潰電場等等。此外，低溫氨氣處理的試片也呈現出較少的二氧化鉿本體內部缺陷(bulk trap)，且對於電壓應力抵抗能力也明顯被改善，即使於高溫的700℃的PDA。最後，我們發現經過電壓應力後，漏電流主要是由於電洞的SILC所主導。 此外，我們也嘗試使用一氧化二氮氣體對二氧化鉿作電漿氮化處理，來改善二氧化鉿閘極介電層的品質。我們發現一氧化二氮電漿氮化處理後，可以得到諸如較低閘極漏電流、較高電導頂峰值(higher peak of transconductor)、較佳次臨界擺幅(substhreshold swing)、較低界面缺陷、和較低二氧化鉿本體缺陷等優點。在二氧化鉿閘極介電層中，電流傳導機制主要是Frenkel-Poole；經過氮化處理後，電子缺陷的能階變深，靠近閘極之傳導帶。我們也發現，在固定電壓應力(CVS)、及負偏壓-溫度應力(NBTI)的可靠性測試中，不管是否經過N2O處理，電晶體之退化，主要是由於本體中之捕捉行為，而非界面缺陷的增加。且經氮化處理後，原本呈現捕捉電洞之行為，會轉變成捕捉電子。在動態應力(dynamic AC stress)可靠性測試下，我們發現，關閉時間(off-time)時釋放電洞之行為，及因開啟時間(on-time)太短，而來不及捕捉電洞，二者均須加以考量，方能解釋動態應力下臨界電壓漂移之行為。透過載子分離(carrier separation)量測，我們得以釐清，崩潰究竟是發生於二氧化鉿本體內部或是界面層。 最後，本論文中，我們探討氟對具有HfO2/SiON閘極介電層之p型電晶體其可靠性的影響。利用氟摻雜在源極/汲極摻雜過程前，然後藉由接下來的高溫摻雜活化過程使氟原子擴散到通道和閘極介電層中去形成氟的併入。發現導入氟對所製造的元件其基本特性沒有明顯的改變，但在固定電壓應力(CVS)和負偏壓-溫度應力(NBTS)測試時，觀察到有氟併入的元件有較低的界面狀態產生和較少的電荷捕捉，因而改善元件的穩定性和可靠性。其次，則是探討電漿效應對具有HfO2/SiON閘極介電層之p型電晶體電性與其對NBTI可靠性的影響，以及氟併入對這些結果的影響也有深入探討。我們發現不論在NBTS前後，界面狀態密度均會隨天線面積比而增加。且負偏壓-溫度應力 (NBTS) 所導致的臨界電壓漂移，也會因受到電漿充電損傷而更加惡化，且其會造成嚴重的電洞缺陷。更重要的是,電漿充電效應會使在二氧化鉿內的的電洞捕捉現象的惡化比界面產生的缺陷更嚴重。這和傳統以二氧化矽為閘極之p型通道電晶體為電子捕捉是不同的。利用氟併入可有效增加對電漿充電損傷的免疫，因此降低具有大天線面積比之元件在NBTS時的嚴重電洞捕捉現象。氟併入仍然維持相同的臨界電壓漂移與界面狀態密度產生的活化能，分別為0.08eV與0.12eV。實驗結果發現，AC電性應力下，臨界電壓漂移會從DC電性應力下的負漂移轉變成的正漂移。這可能是因為在AC電性應力一週期裡的on time時有較少的電洞捕捉及off time時有較多電洞被釋放。此外，AC電性應力下，界面狀態密度產生不易受頻率與duty cycle影響且電洞捕捉現象是ㄧ主要的劣化原因。

As CMOS devices are scaled aggressively into nanometer regime, SiO2 gate dielectric is approaching its physical and electrical limits. The primary issue is the intolerably huge leakage current caused by the direct tunneling of carriers through the ultrathin oxide. To substantially suppress the leakage current, high-k materials are recently employed by exploiting the increased physical thickness at the same equivalent oxide thickness (EOT). In this dissertation, the electrical characteristics of pMOSFETs with HfO2/SiON gate stack subjected various Nitridation, i.e., pre-deposition plasma treatments, post-deposition N2O plasma Nitridation, low temperature NH3 Nitridation, and incorporated with Fluorine were discussed. The related reliabilities, including CVS stress, NBTS, dynamic unipolar AC stress, and charge traping, were comprehensively investigated. In addition, the characteristics of plasma charging damage of the HfO2 high k film few reported and the impact of plasma charging damage on NBTI effects also were studied in detail. Moreover, we also investigate the threshold voltage instability in high k film, due to fast charge trapping at Fast Transient Charge Trap (FTCT), by using the single pulse Id-Vg measurement. First, we investigated the effects of various pre-deposition plasma treatments (NH3 and N2O) on Si surface to form an interfacial layer before deposition HfO2 gate dielectric. In order to significantly reduce gate leakage current, a good quality interfacial layer is essential before deposition of high k film. However, our results show that samples with various gas plasma pre-treatments still result in poor electrical properties and the leakage current does not meet device criterion. A conventional RTA is found to be necessary to repair the damage in the interfacial layer. Samples with plasma pre-treatment and RTA anneal depict lower leakage current, smaller hysteresis and frequency dispersion, and higher breakdown voltage. In addition, NH3 pre-treatment also results in longer time to breakdown, larger charge to breakdown and better characteristics life time. The samples with conventional RTA show much lower leakage current, lower frequency dispersion, and smaller hysteresis than as-deposited, spike RTA and no RTA samples because of a thicker interfacial layer. Therefore, RTA is still an essential process after pre-treatment to densify nitrided interfacial layer. We also found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross section model. In particular, the flatband voltage shift (□Vfb) is mainly caused by the trap filling instead of the trap creation. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode. Second, we proposed a post-deposition low-temperature (~ 400°C) NH3-treatment on the HfO2/SiO2 gate stacks with TiN gate electrode. Our results indicate that samples subject to the LTN treatment exhibit superior C-V characteristics, less frequency dispersion, and lower gate leakage. In addition, the defect density in the bulk and the immunity against trap generations are significantly improved, especially for samples with subsequent 700°C PDA. Moreover, we find that the trap-assisted hole tunneling mechanism is responsible for the increase in gate leakage current after constant voltage stress. Next, we used post-deposition N2O plasma treatment to improve the characteristics of pMOSFETs with HfO2/SiON gate stack. We have found that the improvements include many aspects, such as the reduced leakage current, the better subthreshold swing, the enhanced normalized tranconductance, and the higher driving current. Those were ascribed to the lower interface states and bulk traps, confirmed by various type of charge pumping measurement. In evaluation of the reliability, it was found that the degradation caused by the voltage stress and NBTI was dominated by the charge trapping in the bulk of HfO2 films rather than interface states generation no matter whether the N2O plasma treatment was employed or not. In addition, it was observed that the N2O plasma treatment did significantly improve the charge trapping characteristics and the electron trapping is the main mechanism during stressing, which was opposite to the hole trapping observed in the case without the N2O plasma treatment. Under dynamic AC stress, both the off-time de-trapping and the lack of hole trapping due to short on-time are required to explain the behavior of threshold voltage degradation. Finally, through the help of carrier separation experiments, we have clarified whether the breakdown originates in the bulk or the interfacial layer. Finally, we investigate the effects of fluorine (F) incorporation into HfO2/SiON gate stack on the reliabilities of pMOSFETs with HfO2/SiON gate stack. Fluorine was incorporated before the source/drain implant step, which was subsequently diffused into the gate stack during later dopant activation. We found that F introduction only negligibly impacts the fundamental electrical properties of the fabricated transistors. In addition, under constant voltage stress (CVS) and negative bias temperature stress (NBTS), lower generation rates of interface states and charge trapping are observed for devices with F incorporation, thus enhances high-k devices’ stability and reliability. Next, effects of plasma charging and fluorine incorporation were also explored thoroughly. We find that the interface-state density is increased for devices with large antenna ratio, both before and after the BTS. It is clearly shown that the threshold voltage shift during negative bias-temperature stressing (NBTS) is deteriorated by plasma charging damage, causing severe hole traps, which is different from that observed in traditional pMOSFETs with SiO2 gate dielectric where electron trapping is dominant. More importantly, we also found that hole trappings are aggravated in HfO2 film as compared to interface trap generation by plasma charging. Fluorine incorporation would effectively improve plasma charging immunity, thus reducing the severe hole trapping under NBTS for devices with large antenna area ratios. F incorporation is effective in suppressing hole trapping as well as interface trap generation, thus improving threshold voltage instability. Furthermore, fluorine incorporation maintains almost the same activation energies of threshold voltage shift is 0.08 eV and that of interface trap generation is 0.14 eV for both devices. Fluorine is found to be able to electrically passivate traps without changing the NBTI mechanism. The experimental results of dynamic AC stressing show that threshold voltage shifts toward more negative voltage in DC stress, but shifts toward more positive voltage under AC unipolar stress. This is believed to be due to less hole charge trapping during on-time of a AC cycle and more hole charge de-trapping during off-time of a AC cycle. The interface trap generation depends weakly on both frequency and duty cycle. Instead of interface trap, the bulk trap of HfO2 eventually plays a preponderant role during AC stress.