完整後設資料紀錄
DC 欄位語言
dc.contributor.author蔣亞辰en_US
dc.contributor.authorYa-chen Chiangen_US
dc.contributor.author成維華en_US
dc.contributor.authorWei-Hua Chiengen_US
dc.date.accessioned2014-12-12T02:23:54Z-
dc.date.available2014-12-12T02:23:54Z-
dc.date.issued1999en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT880489077en_US
dc.identifier.urihttp://hdl.handle.net/11536/66111-
dc.description.abstract在使用元件網路所架構的系統裡,對於系統效能而言,資料的傳輸時間是一個很重要的參數,過長的傳輸延遲常會導致系統的不穩定或是資料的毀損。在架構建立一個網路系統時,預測網路上效能的表現是必要的。在本論文中提供一個時序模型去預測資料傳遞的延遲回應來達到預測網路效能的目的,並架構一個實驗用以量測真實情況的延遲以驗證模型所推導出的算式。zh_TW
dc.description.abstractThe time constraint of message transmission plays one of the most important roles on device networks. Response latencies that exceed certain expectation for messages will lead system collapse. It is necessary to predict the operating performance while planning a device network system and accordingly adjust the configuration and parameters of the system. This thesis proposes a time model for the response latency to fulfill the demand and provide an experiment to verify this.en_US
dc.language.isoen_USen_US
dc.subject元件網路zh_TW
dc.subject延遲zh_TW
dc.subject回應zh_TW
dc.subjectDevice Networken_US
dc.subjectLatencyen_US
dc.subjectResponseen_US
dc.title元件網路延遲研究zh_TW
dc.titleStudy on Response Latency of Device Networken_US
dc.typeThesisen_US
dc.contributor.department機械工程學系zh_TW
顯示於類別:畢業論文