應用於正交分頻多工技術為基礎之低複雜度接收端基頻框架同步器

Abstract

在無線通訊的系統中，高速傳輸以及低功率消耗一向是最為關切的兩個研究主題，尤其在近年來發展的超寬頻技術(UWB)中，在接受端的時域同步化需要超過500MHz的頻寬，應用於這樣的高速設計，必需使用平行化架構來作資料處理，同時造成功率消耗的線性成長，使得低功率消成為超寬頻技術發展中最大的挑戰。在本論文中，我們藉由改良的比對濾波器(matched-filter)與動態門檻(dynamic threshold)提出應用於正交多頻分工技術(OFDM)之超寬頻系統的低複雜度框架同步器。在這個設計中，我們使用可以降低比對濾波器複雜度和減少暫存器存取資料次數的演算法來達到低複雜度與低功率消耗的需求，並保持框架同步器的誤差在可接受的範圍之內。此外在平行架構下，不同於一般的設計用多套暫存器存取多重資料流的資料來和多重的比對濾波器作運算，我們基於暫存器共用的觀念，將比對濾波器的資料重新排列後，來讓多重的比對濾波器能夠同時分享一套暫存器的資料，以減少平行架構中所需要的暫存器數量。根據模擬的結果，在802.11a的系統平台，我們提出的設計在10% PER下所造成的誤差小於0.35dB的SNR；而在超寬頻技術的系統平台，我們提出的設計在8% PER下所造成的誤差則是小於0.45dB的SNR。而在硬體的實現上，我們使用.18μm製程，和一般使用平行架構達到528MSample/s的框架同步器相比，我們的設計不但能處理528MSample/s的資料，還可以節省58%的功率消耗和65%的硬體面積

In wireless communication, high data rates and low power consumption are the main concerns to improve the transmission speed and extend the IC working time. In recent years, ultra-wideband (UWB) has received much attention as a high speed, low power wireless portable device. It requires over 500MSamples/s throughput in time domain synchronization and can be achieved by parallel architecture, leading high power dissipation increasing in linear. Therefore, low power issue becomes the challenge of UWB baseband design. In this thesis, a low-complexity frame synchronizer combining improved matched-filter and dynamic-threshold design is proposed for OFDM-based UWB system. It provides a methodology to reduce matched-filter complexity and redundant access of register-files with an acceptable performance loss. Based on the register-sharing algorithm, single register-files shares received data for parallel matched-filters are developed to achieve 528MSample/s throughput for the 480Mb/s UWB design. Simulation results show the synchronization loss of the propose design can be limited to 0.35dB SNR for 10% PER in IEEE 802.11a WLAN system and 0.45dB SNR for 8% PER of LDPC-COFDM and MB-OFDM UWB systems. In hardware implementation, the proposed design can save 58% power consumption and 65% area cost from the conventional design in 0.18μm CMOS process.