高速低密度同位元檢查碼之解碼器設計

Abstract

在本論文中，我們提出了兩個高傳輸速度之低密度同位元檢查碼解碼器的設計。第一個設計為應用於MB-OFDM UWB系統，區塊長度為600之解碼器。此架構採用了對於通道資訊的資料流重新排程以及管線化來減低繞線上的擁擠程度和最長之延遲路徑。經由0.18□m製程實作晶片，我們所提出的此部份平行解碼器設計，於固定8次迴圈的解碼模式下，可提供之最高資料傳輸速度為每秒480Mb。第二個是基於區塊長度為1200之解碼器設計。為了達到更高的晶片密度及降低繞線上所造成的時間延遲，我們所提出的架構採用了一個新的資料重新排序技術，將訊息記憶體和計算單元之間的資料匯流排簡單化。經由此方法，由於晶片密度的提高，我們可大幅的縮減晶片的大小。另外，此解碼器可同時處理兩筆不同之codeword來加快傳輸速度及資料路徑的工作效率。此設計經由0.18□m製程實作後，於晶片面積為21.23mm2，固定8次迴圈的解碼模式下，其最大資料傳輸速度可達到每秒3.33Gb。另外，將此設計經由0.13□m製程實作後，資料傳輸速度可提升到每秒5.92Gb，晶片面積縮小為10.24mm2，而晶片之密度可提高至75.4%。

In this thesis, two high-throughput low-density parity-check (LDPC) code decoders are presented. The first one is a (600, 450) LDPC code decoder applied for MB-OFDM UWB applications. The architecture adopts a re-scheduling data flow for channel values and the pipeline structure to reduce routing congestion and critical path delay. After fabricated in 0.18□m 1P6M process, the proposed partially parallel decoder can support 480Mb/s data rate under 8 decoding iterations. Second decoder is implemented based on a (1200, 720) irregular parity check matrix. For achieving higher chip density and less interconnection delay, the proposed architecture features a new data reordering technique to simplify data bus between message memories and computational units; as a result, the chip size can be greatly reduced due to the increased chip density. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After 0.18□m 1P6M chip implementation, a 3.33Gb/s data rate with 8 decoding iterations is achieved in the 21.23mm2 silicon area. The other experiment using 0.13□m 1P8M technology can further reach a 5.92Gb/s data rate within 10.24mm2 area while the chip density is 75.4%.