標題: 一個適用於直接頻移發射機的雙頻帶四模式和差調變頻率合成器
A Dual Band , Quad Mode Δ-Σ Frequency Synthesizer for Direct Conversion Transmitter
作者: 余岱原
Dai-Yuan Yu
陳巍仁
Wei-Zen Chen
電子研究所
關鍵字: 合差調變器;頻率合成器;Delta-Sigma Modulator;Frequency Synthesizer
公開日期: 2005
摘要: 由於近年來,無線通訊產品的應用越來越普及,所以有許多新的系統因應此潮流而產生,而這些新的射頻系統無不朝向高整合度、低成本、低功率這幾方面發展,也因此本論文將會針對這些目標, 並著重於多模頻率合成器與無線通訊的直接頻移發射器架構部分做設計。 本篇論文設計了一個雙頻帶四模式和差調變頻率合成器,可以產生無線區域網路802.11a、b、g與藍芽系統這四個規格所需要的頻道頻率。整合了相頻偵測器、充電汞、迴路濾波器、壓控振盪器、除二除頻器、多係數除頻器與和差調變器於單一晶片當中。本頻率合成器可以產生2.4GHz~2.5GHz的ISM頻帶頻率與5.15GHz~5.35GHz的UNII頻帶頻率。頻率解析度為1/1024,因此可以滿足四模式的所有頻道頻率。此外,本頻率合成器可以適用於直接頻移發射機系統上,可進行藍芽系統的高斯頻率鍵移調變,並運用數位濾波器的技巧補償鎖相迴路的頻寬以提升發射器的資料傳輸速度。 本晶片使用台積0.18μm互補式金氧半導體的製程,晶片面積為1.98 mm2,功率消耗為19.54mW,頻率合成器在UNII頻帶1MHz頻率偏移處的相位雜訊表現為-117dBc/Hz;在ISM頻帶1MHz頻率偏移處的相位雜訊表現為-120dBc/Hz。此外,本晶片的所有功能機制皆有量測結果做驗證。
The use of wireless products has been rapidly increasing in the past few years, and there has been worldwide development of new systems to meet the needs of this growing market. Therefore , new radio architectures and circuit techniques are being actively sought that achieve high levels of integration and low power operation while still meeting the stringent performance requirements of today’s radio systems. As a result, this paper will focus on these targets and put more emphasis on the design of the multi-band quad mode frequency synthesizer and direct conversion transmitter. This paper describes the design of a dual-band , quad-mode Δ-Σ frequency synthesizer foe WLAN 802.11 a、b、g and Bluetooth application . Integrated a PFD、Charge Pump、VCO、Divide-by-2 Divider、Multi-modulus divider and a Δ-Σ modulator in a single chip . The synthesizer can generate frequencies in 2.4 GHz to 2.5 GHz ISM band and in 5.15 GHz to 5.35 GHz UNII band. The frequency resolution is 1/1024 thus can satisfy all the quad-mode channel frequency specification. In addition , the synthesizer can be used for direct conversion transmitter and can perform the Gaussian frequency shift keying modulation in Bluetooth system. And use digital compensation filter to compensate the phase lock loop bandwidth thus can increase the transmission data rate. The chip is fabricated in TSMC 0.18-um CMOS process and the die area is 1.98 mm2 including pads. The power consumption is19.54 mW from 1.8v power supply .The measured phase noise of frequency synthesizer in UNII band output is –117dBc/Hz @ 1MHz offset and in ISM band output is –120dBc/Hz @ 1MHz offset. In addition, all the function of this chip has been verified by measurement result.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009211598
http://hdl.handle.net/11536/66712
顯示於類別:畢業論文


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