利用複數導數相消之低功率、高線性度混波器

Abstract

本篇論文提出一個複數轉導的等效電路，藉此應用於多閘極架構之線性度分析，相較於之前所提出的分析，此複數轉導能得到更精確之元件參數，以利於電路設計之用。根據此種分析方法，折疊式混頻器與前端電路分別經由晶片製作來驗證。 第一顆晶片在於設計與分析應用於無線區域網路之低功率、高線性度之混頻器。量測結果顯示此一混頻器在只消秏1.8 mW之功率損秏下，有著4.7 dB之轉換增益，9 dB之輸入反迴損秏以及10.3 dBm之輸入第三階交會點。 在第二顆晶片中，適用於無線區域網路接收端之低功率前端電路被設計與分析，此電路包含了一個低雜訊放大器，一個相位分離器以及一個直接降頻混頻器。 量測結果顯示此前端電路有9.5 dB的轉換增益，21.5 dB之輸入反迴損秏以及-2.6 dBm之輸入第三階交會點，此外此電路消秏之功率為10.1mW.

A compact equivalent circuit using a complex transconductance is proposed for linearity design in the multiple gated transistors configuration. This complex transconductance gives better design parameters as compared to previous published analysis. Following the complex transconductance analysis, a folded mixer and a front-end circuit were verified through two individual. In the first chip, a low-power and high-linearity mixer is analyzed and designed for wireless local area network. Measured data shows that the designed mixer has conversion gain of 4.7 dB, input return loss of 9 dB, and input third-order intercept point (IIP3) of 10.3 dBm with only 1.8 mW power dissipation. In the second chip, a low-power front-end circuit, intended for use in the receiver path of the wireless local area network systems, is analyzed and designed. This front-end circuit is composed of a low noise amplifier, a phase splitter, and a direct down-conversion mixer. Measured data shows that the front-end circuit has conversion gain of 9.5 dB, input return loss of 21.5 dB, input third-order intercept point (IIP3) of -2.6 dBm, while consuming only 10.1mW.