針對特殊應用指令集處理器之軟體發展

Abstract

當系統複雜度提高時，為了攤還製造的成本與設計代價，使用可程式化處理器成為相當吸引的設計方式。此外為了滿足現今嵌入式系統嚴刻的效能與功率設計限制，處理器指令集之設計趨向特製於某些應用領域 (即特殊應用指令集處理器)。此篇論文討論如何減低軟體發展時間來加速顆新處理器系統之雛型發展。首先，我們提出一簡單且有效的高階語言編譯機制，藉由在新的處理器核心外包覆一層對編譯器友善的精簡指令集處理器介面，再經由硬體與軟體的協同，編譯精簡指令集處理器程式碼至目標處理器的原生模擬機制也被實作。第二，我們提出一有效率的指令集模擬器，經由分離的危障檢查器與記憶體模擬器可使模擬時間可大幅減少，同時週期準確可由適當的指令插入機制來維持。最後，基於我們的超長指令集數位處理器，我們使用額外6.98%的硬體資源建立一C語言的編譯器和一102~104倍加速的指令集模擬器，此外我們利用所提出軟體工具發展了JPEG 和H.264編碼系統。

Programmable processors are dramatically attractive to amortize manufacturing costs and design efforts, as the system complexity grows. Besides, in order to satisfy the tight design constraints such as performance and power of today’s embedded systems, processor architectures are getting more specialized to some application domains (e.g. an application-specific instruction-set processor; ASIP). This thesis discusses the acceleration of system prototyping of new processor cores by reducing the software development time. Firstly, we propose a simple and effective high-level language compilation method by encapsulation new processor cores in compiler o friendly RISC shell. The native code translation form compiled RISC codes to the target processor is carried out by cooperating hardware and software. Secondly, we propose an efficient instruction set simulator with decoupled hazard checker and memory simulator. The simulation time is significantly reduced via native translation, while the cycle accuracy is maintained with proper instrumentation. Finally, we have constructed a C compiler with 6.98% hardware over head and a cycle-accurate ISS with 102~104 speed up for a proprietary DSP processor. Moreover, we have developed JPEG and H.264 encoding systems based on these software tools.