具有信號處理能力之微處理機的整合性驗證系統

Abstract

從六零年代起, IC 工業依照著著 Moore’s law ( 每十八個月 IC 的容量會增加一倍) 快速地發展. 如此一來, IC 設計的複雜度增高也使得設計驗證更加的困難而延長產品研發週期time-to-market (TTM). 在同時, 一種新的設計方法, 系統單晶片 (SoC) , 它的目的是追求產品設計成本的降低和減少產品研發週期. 所有的矽智財元件被整合在一顆單一晶片中, 如此一來使得系統晶片的驗證更加複雜. 我們需要一個新的, 更有效率, 更加完整性的驗證方法和環境來取代傳統的驗證方式 這篇論文提出一個整合式的驗證系統. 這個整合性的驗證系統是完全自動化而不需要人為的介入. 整個系統由下列幾種構件組成; 自動測試程式產生器可以聰穎地產生測試程式來驗證邏輯設計並追求較高的程式有效涵蓋範圍的分析. 組譯器可以把測試程式產生器所產生的 IAM2000s 的組語程式轉換成 IAM2000s 的程式碼. 而另一個用 RTL所撰寫的比對模組則是用來比較邏輯設計模擬出來的結果和模擬器所執行的結果的正確性. 最後, 測試程式有效涵蓋範圍分析的結果可以用來評判整個邏輯驗證的品質. 這個整合式驗證系統最重要要素的是可以重複使用在驗證其他邏輯電路設計的發展來減少重新建立一個新的驗證系統所耗費的成本支出. 除此之外, 系統單晶片的設計流程可以使用到模擬器加速系統單晶片的開發. 系統單晶片設計者可以將32-bit CPU 核心的行為模型和其他的矽智財元件的行為模型結合成整個系統晶片的行為模型. 系統晶片的軟體開發者可以在此平台上開發軟體應用程式而硬體工程師也能同時利用這個行為模型所產生的正確功能結果來驗證整個系統晶片的功能. 如此一來便能降低系統單晶片的產品研發週期. 在此論文中我們會介紹有關於模擬器的建構和如何利用IAM2000s 核心的行為模型和其他矽智產的行為模型來組成一個真實的系統單晶片的行為模型並實際上利用 traffic light程式來測試整個行為模型.

Since the 60s, the IC industry has made significant progress following Moore’s law: ”the volume of the IC doubles per 18 months”. As a result of the increasing complexity of the RTL design, verify it is difficult and time-to-market (TTM) of products is prolonged. Moreover, System-on-Chip (SoC) solution, a novel design methodology, addresses cost-efficiency. That is, via this methodology, all intellectual property (IP) is integrated into a single system, which also complicates design verification. However, to substitute the traditional verification method and to verify the RTL design a new verification approach is required. In this investigation, an integrated verification system is proposed. The system contains components that are completely automatic. That is, designer‘s intervention is not required. The automatic test program generator (ATPG) produces test vectors that address the higher code coverage analysis. Via ATPG, the assembler can translate the test program to the IAM2000s object code. Another behavioral module compares the results generated both by the behavioral model, simulator, and RTL simulation. Finally, the coverage analysis can be applied to measure RTL design quality. The verification system is reusable for other RTL development to reduce the building cost. In addition, the behavioral model can be applied in the SoC design process. SoC developers combine the 32-bit CPU core behavioral model as well as the behavioral models of additional IPs’ into a SoC system. Thus, to reduce TTM of the SoC products, software and hardware engineers simultaneously develop applications on the platform and verify the RTL design with the integrated behavioral model. Based on the IAM2000s core with additional coprocessors and IPs, a method was developed that constructs the SoC integrated behavioral system.