IAM2000S 系統之AMBA AHB匯流排架構實現與驗證

Abstract

由於半導體製造技術的迅速發展，一個晶片上所能夠容納的電晶體數急遽的增加，使得系統晶片(System On Chip，簡稱SOC)成為晶片設計上的趨勢。系統晶片上能夠整合各種不同功能特性的矽智產 (IP)，因此複雜度也較以往單一功能晶片相對的提升，如何以最有效率的方式來產生最大的用途是SOC的關鍵考量因素。IAM2000S系統的目的是設計一個系統晶片，其中整合了微處理器、記憶體管理單元、寫入暫存器以及晶片匯流排架構，使其能夠在短時間內以其為平台發展嵌入式系統及其應用程式。 重複使用的特性、彈性及模組化的設計、驗證所需的時間、未來的周邊設備的整合度…等特性是在選擇匯流排時考量的課題。AMBA AHB(前瞻微處理器架構之前瞻高性能匯流排)是一個被廣泛運用的晶片匯流排，與其他的晶片匯流排架構相比，其功能受到大眾的肯定及認同，市佔率相當高，並且支援模組化的設計，相當符合IAM2000S系統匯流排(System bus)的需要。 此篇論文提出一個實現AHB匯流排的方法，包含AHB master interface的實現方式、AHB arbiter的演算法及一個用來驗證AHB master interface的匯流排功能正確性的驗證系統，其中的實作經驗及驗證環境可應用至實現其他晶片匯流排上，能夠有效的縮短系統晶片發展的時程並且提高競爭力。

Due to the rapid progress in semiconductor manufacture technology, the continuing increase of the transistor numbers makes SOC (system on Chip) possible to integrate numerous functions onto a silicon chip. An SOC design combines several IP for effective cost and greater performance. IAM2000S system is an SOC platform that combines the processor, memory system and the on-chip bus architecture. In choosing the bus architecture, there are many key topics need to be considered such as the reuse possibility, flexibility and modular design, the verification effort, and the integration period with the time-to-market issue. AMBA AHB is a widely preferred and flexible bus which meets the requirements and its performance has been proven with many complex chip architectures. It has been widely used in the industry and supports modular design, so it can provide shorter system integration period. The contribution of this thesis is to bring up the implementation methodology of AMBA AHB bus and an efficient verification environment on the AMBA AHB master interface. It can be referenced and applied on other bus architecture.