AXI匯流排之系統設計與實現

Abstract

隨著矽智財整合系統單晶片成為可能，整合連結這些矽智財的晶片匯流排成為整個系統效能上重要的角色，Advanced eXtensible Interface(AXI)是新一代的晶片匯流排通訊協定，AXI通訊協定採用封包基準的方式傳輸資料，使用分離的位址與資料通道，每個通道交握方式使用來源的有效信號與目的的就緒信號在時脈正緣取樣，當取樣到兩者的訊號皆是1則完成交握並傳輸資料，因此可簡單插入暫存器增加每個通道管線級數來提高工作頻率，另外還支援不需依序完成、爆發模式傳輸，提供了更高效率的傳輸能力。 在本論文之前並沒有針對新一代晶片匯流排通訊協定上的特性在連結器架構的硬體成本與頻寬的完整探討，目前已存在的AXI匯流排設計都採用交叉開關(Crossbar Switch)架構，雖然交叉開關提供了高頻寬，但也付出了極高的硬體成本，使用共享匯流排架構可以減少許多硬體成本，運用AXI支援不需依序完成的特性在共享匯流排上，仍然可以提供相當高的頻寬，因此我們以SystemC在交換層級(Transaction-level)建構了一個可攜式媒體平台(Portable Media Platform)的模型來模擬分析。 由於AXI匯流排連接器多了一層的暫存器，交握時為了確保資料傳輸正確，在一般的傳輸模式下頻寬的最高使用率只有50%，針對這點在本篇論文我們設計了交錯傳輸模式(Interleaved Mode)來提高頻寬使用率最高達99%。此模式的使用只要連接器提供支援即可，完全不需要協定上的修改。此外，對於系統中有高初始延遲的記憶體控制器裝置，我們另外設計了資料通道鎖定模式(Data Lock Mode)以及混合傳輸模式(Hybrid Mode)，可以有效地減少記憶體資料傳輸時間，也給予記憶體控制器高度重新排程的能力，以提高頻寬使用率並進而提昇系統的效能。 在建構的平台上我們驗證了所提出的各種傳輸模式在真實系統環境下的效用，除此之外，實驗中探討了AXI介面緩衝器大小、仲裁策略、傳輸模式以及仲裁權重調整方式對系統效能的影響，實驗結果證明在適當傳輸模式配置和系統配置下，可以提高69%的頻寬使用量、進而提升40%的系統速度。另外相較於傳統不支援不需依序完成功能的匯流排如AHB，AXI匯流排搭配前述提出的傳輸模式與系統配置，最多可以提高346%的頻寬使用率及44%的系統速度。這顯現出採用AXI匯流排並恰當地搭配各種傳輸模式可以大幅度並有效地改善系統效能。 最後我們做成實際的硬體，在0.13微米的互補式金氧半導體製程下，在200百萬赫茲的運作頻率下需要18.85K個邏輯閘，提供使用每一千個邏輯閘每秒84MB的頻寬。

The on-chip-bus (OCB) which connects silicon intellectual property (SIP) in a system-on-a-chip (SoC) plays a key role in affecting the system performance. Recently, a new generation of packet-based OCB protocol called Advance eXtensible Interface (AXI) has been proposed. The AXI separates the address and data into independent channels. The handshaking of each channel uses two signals which one is VALID from source and the other is READY from destination. Once the VALID and READY are high at the same clock positive edge, the handshaking completed and data transferred. Therefore, it is easy to add pipeline stage to increase operating frequency by inserting the register slice. Besides, the AXI protocol supports out-of-order completion and burst-based transaction to provide more bandwidth than traditional OCB protocol. Before this thesis, there is no complete analysis on the interconnect architecture and bandwidth of the of new generation OCB protocol. The existed AXI bus interconnect all adopt the crossbar switch as the architecture. Although the crossbar switch provides high bandwidth, it needs extreme hardware cost. Using the characteristic of AXI, we can adopt the shared bus as the architecture of the bus interconnect to obtain low hardware cost and keep fairly high bandwidth. To analyze impact of the architecture, a portable media platform (PMP) is modeled at transaction-level with SystemC for simulations. However, the AXI bus interconnect can only achieve 50% of bandwidth utilization at most when normal transfer mode is being used. Therefore, we propose an interleaved transfer mode to increase the bandwidth utilization up to 99%. The interleaved transfer mode can be implemented as a totally built in feature of a bus interconnect and does not need any modification to the protocol. In addition, this work also proposes a data lock transfer mode and hybrid mode to handle the transactions to the devices with long initial access latency, such as the memory controller in a system. These modes decrease the transfer time and give the memory controller a higher degree of access rescheduling capability. We evaluate impact of the proposed transfer modes in the portable media platform. In addition, the impact of wrapper buffer size, arbitration policy, transfer mode setting, and arbitration parameter settings are also studied. The simulation result shows that the proposed transfer modes improve the bandwidth utilization by 69% and speed up the system by 44%. Compare the performance with the traditional bus such as the AHB; the AXI system can outperform the AHB system in bandwidth utilization by 346% and system speed by 44% at most. The implemented AXI bus interconnect with the proposed transfer modes has a gate count of 18.85K when synthesized with 0.13μm CMOS process under 200 MHz operating frequency.