架構於AMBA系統上之MPEG-4即時影像編碼器設計

Abstract

在本篇論文中，我們實現了一個高效率的MPEG-4 Video Encoder的硬體架構。在此MPEG-4 Video Encoder中，我們提出了Motion Estimation及Variable Length Coding的硬體加速架構。在Motion Estimation方面，可達到只需要495個時脈週期就可找出一個Motion Vector的效率，以及有效的減少On-Chip Memory的使用量；而在Variable Length Coding的部分，它可以和Motion Estimation及Texture Coding平行處理，可達到1個時脈週期輸出1個Symbol的編碼效率。在整個Video Encoder整合的部分，我們也將說明如何對整個系統做排程，以達到即時影像壓縮的需求。 此MPEG-4 Video Encoder是定位在一個coprocessor的地位，目的在協助嵌入式處理器處理運算量龐大的影像壓縮工作，因此，此IP (Intellectual Property)是以IP 重覆使用及Platform Independent的概念進行設計，它由內部暫存器控制其行為，IP使用者只需要更改IP的wrapper就可以將此IP加到特定平台中使用，避免掉各種匯流排通訊協定不同的問題。AMBA是目前嵌入式系統最常使用的匯流排架構，我們將此IP嵌入到AMBA Bus上，搭配自行開發並相容於AMBA通訊協定的DMA controller，在ARM Integrator上做FPGA 驗證，證明此IP在AMBA系統上的功能正確性。

In this thesis, a high-performance MPEG-4 video encoder is proposed. In this system, an enhanced hierarchical motion estimation algorithm and an efficient variable length coding hardware architecture are presented. The motion estimation algorithm can reduce the search cycles to 495 cycles/MB(Macro Block) and can reduce the memory usage efficiently. The variable length coding architecture can execute the entropy coding parallel with other components such as motion estimation and texture coding to improve the whole encoder system performance. In addition to these hardware blocks, how the system is scheduled to achieve the pipeline execution of each component will be explained. This encoder is designed to be a coprocessor that can help the embedded processor to handle the data processing. Therefore, this processor is designed on the IP reusing and platform independent concept. The only thing that the users have to do is to modify the wrapper for specific platform. This IP is wrapped in the AHB bus system and its functionality is verified on the ARM Integrator. Besides, an AMBA 2.0 compatible DMA controller is developed to move the image data to improve the system performance.