具有信號處理能力的嵌入式微處理機之仿真機制設計與實作

Abstract

隨著電子資訊技術日新月異，快速上市將是產品是否成功的關鍵，而如何縮短設計時程一直是個重要的問題。當開發一個應用系統時，我們常藉由使用仿真器(ICE：in-circuit emulator)來加快除錯的工作，進而減少系統開發所需的時間。但是，由於一般處理器在設計時，並沒有考慮支援仿真器的硬體設計，使得仿真器的設計變得複雜且費時，因而降低產品開發的效率。而且，隨著單晶片系統時代的來臨，處理器內嵌於晶片中，使得傳統的仿真器方法已不可行。因此，我們使用一個方法來改善，也就是在設計處理器時，考慮在處理器中加入支援仿真器的電路，以方便仿真器的開發及晶片除錯的工作。 在這篇論文中，我們在處理器內設計額外的硬體以支援仿真器，這部分額外的電路能讓使用者設定欲觀察的中斷點、控制處理器的運作，並觀察處理器與系統的狀態。為減少晶片的接腳數，我們並把這部分硬體與IEEE Std 1149.1整合，使用JTAG邊緣掃瞄的原理來降低必須增加的腳位數量。最後，我們將此設計實作在IAM 2000S上，並評估增加這些額外硬體所付出的代價。

With the rapid development in electronics and information industry, fast time-to-market plays an important role in product success. Therefore, to shorten the design cycle is a matter of concern today. Using a in-circuit emulator (ICE) is usually the method we adopt to help debug our design when developing an application system. In the traditional processor design, there is no in-circuit emulation in mind. This complicates the design of in-circuit emulators and thus delays the whole development cycle. Besides, the traditional in-circuit emulation strategy is impractical in the upcoming system-on-chip era since the processor is embedded into a chip. There must be some evolution in the design to improve this situation. In the thesis, we introduce a design tactic to help solve the problem. That is, we add some hardware features into the processor to ease the ICE design. The hardware we added is called the embedded ICE (eICE). The eICE enables users to set breakpoints, control the processor's execution, and observe the state of the system. We also integrate the eICE with the boundary scan test to reduce the increase of the necessary pin count. Finally, the eICE and the boundary scan test logic is implemented in the IAM 2000S. The cost of the extra hardware is also evaluated.