應用於超寬頻系統之可調頻低雜訊放大器

Abstract

本篇論文主要是利用標準0.18µm CMOS製程設計應用於超寬頻系統前端接收器之可調頻低雜訊放大器。第一顆晶片，設計適用於接收端超寬頻系統之可調頻率放大器被設計與分析，利用柴比雪夫濾波器設計達到寬頻之輸入阻抗匹配，利用電晶體可變電容來調變頻率。量測結果顯示可調變頻率範圍縮小，且操作頻率往低頻移動，可調頻率為5.1GHz 到 6.8GHz有最高功率增益(S21) 7.4dB，以及最低雜訊指數5.7dB，消耗之功率為19.51mW。依據第一顆晶片量測結果，經過驗證反察，發現可變電容的容值比預期大且可調變範圍比預期小，原因出在模擬的可變電容模組和所佈局的模組不同而產生，因此，第二顆晶片修正可變電容模組，且加上切換MIM電容，增加可調頻率範圍；並改用諧振匹配原理達到輸入寬頻阻抗匹配，降低雜訊指數和功率消耗，修正晶片量測結果顯示，可調頻率為6.3GHz到9.4GHz，最高增益9.3dB，發生在9.4GHz，平均雜訊指數為4.5dB，消耗功率為17.44mW。接著為了達到3GHz 到8GHz之超寬頻可調頻率，考慮可變電容之可調範圍的先天限制，因此，第三顆晶片結合MEMS電感的高Q特性，設計切換電感負載，達到更寬頻之調頻設計。比較前兩顆切換MIM電容和第三顆切換MEMS電感的LNA設計，MEMS高Q特性的優勢，明顯使電路達到高增益且超寬可調頻率，及低雜訊，低功率的設計目的。

The objective of this thesis is aimed at design of low noise amplifier (LNA) with tunable output frequency for the ultra-wideband (UWB) receiver system using standard 0.18um CMOS process. Three LNA circuits have been implemented. In the first chip, a wideband tunable low noise amplifier is analyzed and designed using the Chebyshev filter design to achieve broadband input impedance matching and a MOS varactor provides frequency tuning capability. The measured data show that the tunable frequency range is from 5.1GHz to 6.8GHz, narrower and lower as compared to the designed values. The frequency drift is due to the inconsistency of the varactor models in the circuit simulator and the circuit layout. Therefore, the second chip is designed to revise the tunable mechanism. The measurement data of the second chip shows that the frequency tunable range is 6.3GHz to 9.3GHz. To extend the tunable frequency range to 3GHz to 8GHz and still maintain the high power gain is limited by the poor quality factor of the large MIM capacitor value. Therefore, the high Q micromachined inductors are integrated with the third chip to achieve the wideband tunable range and good noise performance. Furthermore, power consumption is reduced by an external capacitor placed across the gate and the source ports of the input transistor.