在網路處理器上實作差別服務時所衍生出之延展性和瓶頸之探討

Abstract

網路處理器已漸漸成為傳統以ASIC為主用來處理使用者平面封包的另一可程式化的選擇。它利用其共同處理器(co-processors)協助處理原本一般用途處理器(general-purpose processor)所負責的使用者平面的封包。在本論文中，我們將描述將差別式服務邊緣路由器(DiffServ edge router)實作於IXP1200網路處理器的流程，並探討其效能。IXP1200網路處理器具有一個處理控制平面的StrongARM核心處理器(core processor)和六個共同處理器，並將分類(classification)和排程(scheduling)的規則寫在SRAM，封包則儲存於SDRAM。根據外部測試顯示，就一條輸入埠(input port)而處理能力(throughput)為50Mbps時，本系統可以支援符合個別行為(Per-Hop Behavior)的500個資料流(flow)，且可隨著SRAM的增加而繼續擴充。經由內部測試我們發現效能瓶頸(bottleneck)會隨著不同的服務和實作而轉移到不同的地方。就簡單的遞送服務(forwarding service)而言，SDRAM為一當然瓶頸。然而當涉及眾多的規則表查詢和計算時，SRAM和microengine則分別成為其效能瓶頸。另外，我們也指出了IXP1200硬體設計的可能缺失，稱之為”媒體存取控制緩衝儲存器的問題” (MAC buffer problem)。

Network processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the user-plane processing of network services. They serve as co-processors to offload user-plane traffic from the original general-purpose microprocessor. In this work, we illustrate the process and investigate performance issues in prototyping a DiffServ edge router with IXP1200, which has one control-plane StrongARM core processor and six user-plane microengines, and stores classification and scheduling rules at SRAM and packets at SDRAM. The external benchmark shows that the system can support an aggregated throughput of 141Mbps of eight input ports, and 500 flows, which is extensible provided enough SRAM space, at one input port while conforming the PHB of each flow. Through internal benchmarks, we found that performance bottlenecks may shift from one place to another given different network services and implementations. For simple forwarding services, SDRAM is a nature bottleneck. However, it could shift to SRAM or microengines if involving heavy table access or computation, respectively. We also identify the design pitfall of the hardware called the “MAC buffer problem”.