低電壓差動訊號傳輸標準之平面顯示器資料接收器設計

Abstract

隨著平面顯示器尺寸不斷地增加，顯示器所提供的色彩濃度與解析度也不斷地提升。解析度SVGA (800 600像素) 和XGA (1024 768 像素) 已是平面顯示器最基本的要求。解析度不斷地提升，同時也意味著資料傳輸量與資料傳送速度的提升。尤其以位於平面顯示系統裡，直接連接顯示卡到液晶顯示時脈控制器之間的資料傳送遇到的瓶頸最為明顯。在高速的資料傳送速度下，如何正確地傳送資料成為一個值得研究的課題。本論文將提出一個應用於平面顯示系統低電壓差動訊號接收器的新架構，提升資料接受器對訊號偏移量的忍受度，同時降低整個電路的複雜度，達到提高資料接收效率並節省成本的效果。本文提出的新架構主要分成兩個部份，第一部份中提出三倍四分之一步距取樣 ( Three quarter steps oversampling ) 架構來提升接收器對輸入訊號眼圖 ( eye diagram ) 的忍受度。第二部份提出延遲選擇 ( Delay selecting ) 架構來降低整個接收器佈局的複雜度。 傳統接收器架構中，大多使用三倍取樣 ( Three times oversampling ) 架構來恢復輸入訊號。當輸入資料偏移量接近二分之一步距時，三倍取樣架構將無法分辨出偏移量是領先還是落後取樣時脈，因此可能造成恢復資料的出錯。本文提出的三倍四分之一步距取樣中，因為存在一個取樣點落在取樣步距二分之一處，所以在資料偏移量小於二分之一步距下，三倍四分之一步距取樣架構皆能判斷出資料偏移的方向，達到提升對眼圖的容忍度。第二部份的延遲選擇架構取代傳統電路中的相位選擇 ( phase selecting ) 架構。傳統的相位選擇架構搭配三倍取樣架構，在平面顯示系統低電壓差動訊號接收器的應用中，需要使用21個不同相位的取樣時脈，如此一來將增加電路佈局的複雜度，連帶造成佈局面積的膨脹。新架構中因為使用延遲選擇架構取代相位選擇架構，整個電路中只需要使用到7個不同相位的取樣時脈，大幅減低佈局的複雜度，同時縮小整個佈局面積達到降低成本的目的。

As the size of flat panel displays increasing, flat panel displays offer higher color depth and resolution. Offering the SVGA (800 600 pixels) and the XGA (1024 768 pixels) resolutions becomes a basic requirement of flat panel displays. The increase of display resolution also means the increase of data rate. Especially at the interfaces that directly connect a graphics card to a liquid crystal display’s (LCD’s) timing controller in FPD systems, the high-speed data rate becomes a serious bottle net. When the resolution is up to SXGA (1280 1024 pixels) and UXGA (1600 1200 pixels), the data rate is up to 784 Mbps and 1155 Mbps. How to recover data correctly in the high-speed data rate becomes a significant topic. This thesis is going to present a new architecture of receiver with the LVDS standard for FPD application, which increases the tolerance of the skew between signals and reduces the complexity of the layout. The new architecture not only increases the performance but also reduces the cost. There are tow parts of the new architecture presented in this thesis. First part presents the “three quarter steps oversampling” system, which increases the tolerance of the eye diagram of input data. Second part presents the “delay selecting,” which reduces the complexity of the layout. In traditional architecture, most receivers use the “three times oversampling” system to recover input data. However, when the skew between input data and the input clock is close to half step time, the “three times oversampling” system can not detect whether the skew leads or lags, and may induce errors in recovered data. Because there exists a sampling clock phase at the center of data step in the “three quarter steps oversampling” presented in this thesis, the “three quarter steps oversampling” system can detect whether the skew leads or lags when the skew between input data and the input clock is close to half step time. Thus, by using the new system the receiver can increase the tolerance of the eye diagram of input data. The “delay selecting” presented in the second part is used in the receiver instead of the “phase selecting,” which is usually used in traditional architecture. Using the traditional “delay selecting” and “three times oversampling” system in the receiver for FPD applications, it needs 21 differential sampling clock phases to sample input data, and that will increase the complexity of layout and induce the expansion of the layout area. Because the new architecture uses the “delay selecting” instead of the “phase selecting”, it only needs 7 differential sampling clock phases during recovering input data, and that actually reduces the complexity and the area of the layout and reduces the coast of the receiver.