先進深次微米金氧半場效電晶體基極與閘極工程之研究

Abstract

在本論文中，我們針對深次微米元件的基極與閘極部分進行研究，涵蓋的內容包括銦所形成的超陡峭通道雜質分佈元件，動態臨界電壓場效電晶體，絕緣層上矽元件以及利用閘極堆疊犧牲層製程來改善P型場效電晶體硼穿透的問題。 研究發現銦超陡峭通道元件相較於傳統硼摻雜通道元件，有較高的線性區轉移電導以及較低的飽和驅動電流。此外，銦摻雜通道元件在DIBL，Ion-Ioff電流比率以及電晶體崩潰有較佳的特性。最後，我們發現增加銦原子離子佈植能量，元件漸有較佳的轉移電導，DIBL以及熱載子免疫力。然而，卻有較大的接面漏電流及接面電容。在另一方面，我們首次發現在不同銦離子佈植能量下，異常的臨界電壓交差現象。我們提出一個一致性的結論，銦原子de-activation 會抑制暫態增強擴散效應。 利用銦超陡峭通道完成的80nm通道長度動態臨界電壓場效電晶體於0.7伏電壓操作下，驅動電流達348mA/mm (漏電流40nA/mm)，高記錄的轉移電導 Gm = 1,022 mS/mm 以及74 mV/dec的次臨界波動。我們首次發現In-DTMOS有較佳的熱載子免疫力。 LOCOS絕緣下的SOI電晶體的窄通道效應方面，研究中發現在較薄的矽厚度元件上，反向窄通道效應較趨緩。我們提出一個解釋，在電晶體通道寬度方向的氧化層/矽介面面積的減少，因此快速在介面復合的矽interstitials減少，而使硼原子擴散至場氧化層較少。此外，研究中發現利用氮植入通道可以減少反向窄通道效應。 最後我們提出一個新穎的製程利用閘極堆疊犧牲層(TEOS)來製作具有BF2離子植入形成的源/汲極延伸區的P型金氧半場效電晶體。因為摻入的氟原子被捕捉在TEOS犧牲堆疊層中，因此硼穿透的程度有效的減少。利用此新製程，元件有較好的特性以及氧化層可靠度的提高。

In this dissertation, we investigated the substrate and gate engineering of deep sub-micron MOSFETs including indium super-steep-retrograde (SSR) channel devices, Dynamic Threshold MOSFET (DTMOS), silicon-on-insulator (SOI) MOSFETs and sacrificial gate stack process to reduce the boron penetration issue on pMOSFET. It was found that devices with super-steep-retrograde (SSR) indium channel profile depict higher transconductance in linear region, and the saturation drive current is lower, compared to the conventional BF2-doped control. In addition, In-doped devices also depict improved DIBL, Ion-Ioff current ratio and transistor breakdown voltage. Finally, by increasing the indium implant energy, devices depict an improved transconductance, reduced DIBL and hot-carrier degradation, while suffering larger junction leakage and capacitance. In the other hand, an anomalous crossover in Vth roll-off curves was observed, for the first time, on indium-implanted splits with different implant energies. This phenomenon can be consistently explained by the suppression of transient enhanced diffusion (TED) of channel impurity due to indium deactivation. 80nm-gate-length Dynamic Threshold Voltage MOSFET (DTMOS) were fabricated using indium super steep retrograde channel implantation exhibiting drive current as high as 348mA/mm (off-state current 40nA/mm), a record-high Gm = 1,022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7V operation. Moreover, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS. Deep submicron silicon-on-insulator (SOI) nMOSFET’s with LOCOS isolation have been investigated. A thinner silicon film is found to depict less threshold voltage fall-off. A reduced oxide/silicon interface area in the transistor width direction can explain these results, thus the boron segregation due to silicon interstitials with high recombination rate is reduced. In addition, the reverse short channel effect (RSCE) is also suppressed by the nitrogen channel implant. In the final part, we report a novel process flow with sacrificial tetraethyl orthosilicate/polycrystalline silicon (TEOS/poly-Si) gate stack for fabricating p-channel metal oxide semiconductor field effect transistors (p-MOSFETs) with shallow BF2-implanted source/drain (S/D) extension. The incorporated fluorine atoms are trapped in the sacrificial TEOS top layer, the deleterious boron penetration through the gate oxide is therefore alleviated. Devices fabricated with the novel process indeed show better transistor performance and improved gate oxide integrity.