神經元雙載子接面電晶體及其在類神經網路設計之應用

Abstract

在本論文中，主旨在於闡述一個可用來實現超大積體電路神經網路之新型神經元雙載子接面電晶體元件的分析與設計，並由其在類比式赫米神經網路與細胞神經網路上之應用加以驗證。整篇論文可分成三大主要分: (1) 神經元雙載子接面電晶體為架構之分析與設計及其應用在類比式赫米神經網路之製作; (2) 具有大鄰近層數對稱模版可程式化神經元雙載子接面電晶體細胞神經網路之製作; (3) 具有大鄰近層數不對稱模版可程式化神經元雙載子接面電晶體細胞神經網路之製作。 首先，本論文提出神經元雙載子接面電晶體架構，其中神經元部分是利用互補式金氧半製程中的寄生PNP雙載子接面電晶體來實現，而對於不同輸入所對應的神經鍵權值則是利用基極的分佈電阻陣列來實現，雙載子接面電晶體多射極的架構同時能被用來產生神經元的多輸出極，因此，這個神經元雙載子接面電晶體細胞具有小的晶片面積與架構密集的優點，它已經能成功的被應用在類比式赫米神經網路的製作上。這個類比式赫米神經網路能夠儲存許多套不同灰度的圖案樣本，此外，利用輸入圖案的加權或縮放比例可以消除共模抵補訊號和增加訊號的動態範圍並能增加對處理訊號能力的可靠度。一個以0.6微米互補式金氧半製程技術所設計與製作的8x8細胞陣列大小類比式赫米神經網路晶片，已由量測的結果成功的驗證了它的功能。因此，所提出的神經元雙載子接面電晶體類比式赫米神經網路將有很大的應用潛力。 其次，根據這個神經元雙載子接面電晶體基本的元件物理，我們提出並分析另一個新型緊密神經元雙載子接面電晶體細胞神經網路架構。在這個新型的神經元細胞神經網路中，利用互補式金氧半製程中寄生PNP雙載子接面電晶體所形成之神經元及lambda雙載子接面電晶體來現實神經元，而對於神經元間的對稱神經鍵權值則是利用N型金氧半電晶體來製作，因此它同樣具有小的晶片面積與架構密集的優點。另外，所提出的這個對稱模版的神經元雙載子接面電晶體細胞神經網路，它可以很容易在不增加接線的情形下完成大鄰近層數設計。這是第一個製作出具有大鄰近層數的超大積體電路細胞神經網路。其次，可以在雙載子接面電晶體上面加裝一個金屬照光的窗口，這樣雙載子接面電晶體就可以當作光電晶體來使用，光電晶體可以接收光影像來當作初始狀態或外部輸入訊號。神經元雙載子接面電晶體細胞神經網路已在消除雜訊、空洞的填裝與侵蝕等功能，由HSPICE成功的驗證出。包括32□32細胞陣列大小的神經元雙載子接面電晶體細胞神經網路和具有光電晶體的16□16神經元雙載子接面電晶體細胞神經網路實驗晶片已由0.6微米互補式金氧半製程技術設計與製作出。根據量測結果顯示，此晶片的每個基本單元的轉態時間是0.8微秒和有60微瓦的靜態功率消耗，並且有高達每釐米平方1270基本單元的面積密度。量測結果更堅信所提出之神經元雙載子接面電晶體細胞神經網路功能的正確性。 最後，我們提出並分析另一個具有大鄰近層數不對稱模版的新型緊密神經元雙載子接面電晶體細胞神經網路架構，相同於前面的架構，利用互補式金氧半製程中寄生PNP雙載子接面電晶體所形成之神經元及lambda雙載子接面電晶體來現實神經元，而神經元間的不對稱神經鍵權值則是利用兩個共極放大器的可程式化級來實現，共極放大器是由兩個閘極控制的側生PNP雙載子接面電晶體、兩個金氧半電晶體開關和一個耦合金氧半電晶體電阻所組成。單鄰近層數神經元雙載子接面電晶體細胞神經網路在邊緣偵測、陰影投射與連接成分偵測等正確的功能已由HSPICE成功的加以驗證。另外，所提出的雙載子接面電晶體細胞神經網路可以更進一步被修正在不增加太多額外接線與電路的情形來實現大鄰近層數細胞神經網路。三個大鄰近層數細胞神經網路例子在等角偵測、解濛朧與箭頭幻覺等正確的功能已經由HSPICE成功的驗證。0.6微米互補式金氧半製程技術設計與製作一個單鄰近層數不對稱模版16□16細胞陣列大小的細胞神經網路實驗晶片。根據量測結果顯示，此晶片的每個基本單元的轉態時間是1微秒和有264微瓦的靜態功率消耗，具有每釐米平方236基本單元的面積密度。量測結果更堅信所提出之雙載子接面電晶體細胞神經網路功能的正確性。 從上面得驗證結果，本論文所發展出的神經元雙載子接面電晶體神經元架構對於實現類神經網路系統在不同訊號處理應用上具有極大的潛力，未來將朝這個領域繼續研究。

In this thesis, a new device called the neuron-bipolar junction transistor (vBJT) is proposed and analyzed for VLSI implementation of neural networks. The applications of vBJTs on analog Hamming neural network and cellular neural networks (CNNs) are also presented and verified. The whole thesis is divided into three main parts: (1) the analysis and design of the vBJT structure and its application to the implementation of the analog Hamming neural network; (2) the implementation of the new vBJT CNN structure with programmable large-neighborhood symmetrical templates; (3) the implementation of the new vBJT CNN structures with programmable large-neighborhood asymmetrical templates. Firstly, in the proposed vBJT structure, the parasitic PNP bipolar junction transistor in the CMOS process is used to implement the neuron whereas the spreading base resistor array is used to realize the synaptic weights for various neuron inputs. The multi-emitter structure can also be used to realize the multiple neuron outputs. The vBJT neuron cell has the advantages of compact structure and small chip size. The vBJT neuron cell has been successfully applied to the implementation of the analog Hamming neural network. The analog vBJT Hamming network can store many sets of examplar patterns with different gray levels. Moreover, the levels of input patterns can be weighted or scaled to eliminate the common offsets and increase both input dynamic range and processing flexibility. An experimental chip of the proposed vBJT analog Hamming neural network with the cell size of 8x8 has been designed and fabricated by using 0.6um single-poly triple-metal (SPTM) N-well CMOS technology. The analog Hamming neural network has been successfully verified through measurement. With simple and compact structure and high integration capability, the proposed vBJT Hamming network has a great potential in various applications. Secondly, based on the basic device physics of the vBJT, a new compact CNN structure called the vBJT CNN, is proposed and analyzed. In the vBJT CNN, both vBJT and lambda bipolar transistor realized by parasitic pnp BJTs in the CMOS process are used to implement the neuron whereas the coupling MOS resistors are used to realize the symmetrical synapse weights or templates among various neurons. Thus it has the advantages of small chip area and high integration capability. Moreover, the proposed symmetrical vBJT CNN can be easily designed to achieve large neighborhood without extra interconnection. This is the first realized analog large-neighborhood CNN VLSI. By adding a metal-layer optical window to the vBJT, the □BJT can be served as the phototransistor and the vBJT CNN can receive optical images as initial state inputs or external inputs. The correct functions of the vBJT CNNs in noise removal, hole filling, and erosion have been successfully verified in HSPICE simulation. An experimental chip containing a 32x32 vBJT CNN and a 16x16 vBJT CNN with phototransistor design, has been designed and fabricated in 0.6um single-poly triple-metal N-well CMOS technology. The fabricated chips have the cell state transition time of 0.8us and the static power consumption of 60 uW/cell. The area density can be as high as 1,270 cells/mm2. The measurement results have also confirmed the correct functions of the proposed vBJT CNNs. Finally, the new vBJT CNN structures with asymmetrical templates and large neighborhood are proposed and analyzed. In the proposed vBJT CNN, the structure of vBJT is incorporated with that of the lambda bipolar transistor (vBJT) and realized by parasitic pnp BJTs in the N-well CMOS technology to implement the neuron. The synaptic weights are realized by a fully programmable stage containing two common-emitter amplifiers formed by two gate-controlled lateral pnp BJTs, two MOS switches, and one coupling MOS resistor. The correct functions of the vBJT CNNs with single neighborhood in edge detection, shadow projection, and connected component detection have been successfully verified in HSPICE simulation. Moreover, the proposed vBJT CNN is further modified to implement large neighborhood without adding too many extra interconnections and circuits. As the demonstrative examples on the applications of the proposed large-neighborhood vBJT CNNs, three function of corner detection, de-blurring, and muller-lyer arrowhead illusion have been successfully realized and verified by HSPICE simulation. An experimental chip of 16x16 vBJT CNN with asymmetrical templates and single neighborhood layer has been designed and fabricated in 0.6um single-poly triple-metal N-well CMOS technology. The fabricated chips have the cell state transition time of 1us and the static power consumption of 264uW/cell. The cell density can be 236 cells/mm2. The measurement results have confirmed the correct functions of the proposed vBJT CNNs. From the above results, it is believed that the proposed □BJT structure has a great potential in the implementation of neural network systems for various signal processing applications. Further researches in this field will be conducted in the future.