快速跳頻系統使用之基頻接收器

Abstract

無線個人區域網路(WPAN)會帶給人類無限方便，眾所周知。諸多研究，如藍牙技術的研究，已投入大量人力、物力，為的就是加強無線網路技術及其功能。相較於其它無線通訊網路系統，無線個人區域網路更需要具備高度安全的通訊機制及高系統的容量。面對這兩大問題，最適合的解決方法，就是在系統實物層面設計時，利用快速跳頻的無線網路技術。 快速跳頻系統的研發設計雖已略有成效，仍有不少困難需要解決，如時間回復(Timing Recovery)、頻率合成器都是不容易設計的電路。以下針對於這兩項分別說明其設計上之困難以及本論文提出的解決之道： 1. 傳統快速跳頻系統中的時間回復電路，需要量測接收到訊號的強度，來判斷時間誤差。而量測接收到訊號的強度，不是要較高的類比電路設計技巧，就是需要複雜的數位電路，於是我們嘗試採用不需要訊號強度的方式去做時間回復。 2. 同時具有快速轉換頻率以及大頻寬的頻率合成器也是難以設計，最近幾年來有許多研究報導能夠達到快速頻率轉換以及提供出很大頻寬的頻率合成器設計，但這些設計不是需要使用到隨機取樣記憶體，就是會在頻率轉換時出現許多雜訊。因此，本論文研究嘗試用函數來描述輸入震盪器的控制訊號以及震盪器所震出的頻率，利用這樣的描述就可以描述出不同的震盪器狀態。因為掌握了震盪器的狀態，就能夠達到以零採集時間執行快速跳頻。 此外，在設計這些電路的過程中，需要經過系統模擬的驗證。採用傳統方式模擬整個系統需要耗費很長時間，增加研發測試的時間。然而，重新整理模擬系統的數學方程式，並加以化簡，就可以使得系統模擬更有效率。這樣的一個有效率的系統模擬除了可以節省時間，還能寫成Verilog硬體模擬語言，以便於在Verilog的邏輯閘層級(Gate Level)中驗證電路的正確性。

Wireless Personal Area Network (WPAN) technology can bring more convenience into our future lives. The importance of WPAN can be seen from the vast amount of energy spent on developing WPAN related technology such as Bluetooth, 802.15, etc. WPAN technology requires better security and greater system capacity than other wireless technologies. Therefore, fast frequency hopping system is the most suitable physical layer system for WPAN technology. Although there are several accomplishments in the design of fast frequency hopping systems have been achieved, there are still several difficulties to over come. First of all, in a conventional fast frequency hopping system, timing recovery requires knowledge of received signal energy. Recent researches on timing recovery for fast frequency hopping requires either advanced analog circuit design or complicated fast digital circuits. In this thesis, new timing recovery method without the need of received signal energy is experimented. Second, it is difficult to design a fast frequency switching frequency synthesizers with large output frequency bandwidth. By modeling oscillators into functions, the frequency synthesizer can switch different frequency with zero acquisition time. During the development of the proposed circuits in this thesis, system simulations are required to ensure the correctness of the developed circuit. It was found that using the conventional way to simulate the entire frequency hopping system is time consuming and inefficient. After several derivations, it was found that by simplifying several equations, a more efficient channel model could be derived. This channel model not only saved time, but also was able to be written into Verilog code for gate level code verification.