電流交替式混頻器的研究

Abstract

無線通訊的各項需求推動著前端模組的研究, 混波器乃是前端電路中很重要的一個要件。在此論文中, 我們的討論將著重於電流交替式混波器之雜訊以及線性度的討論, 分析討論的標的將是CMOS的Gilbert cell。我們提出一個數學上的模型, 它可直接將雜訊以及線性度的表現與設計參數, 如偏壓以及元件大小等, 作一個直接的連結。藉由模擬結果, 我們可以驗證此數學模型預測的準確度, 而我們的確得到一個不錯的趨勢預測。電流交替式混波器在各項性能上皆相互存在好壞的取捨, 關於這方面, 我們亦作了一些約略的分析。 為了縮短設計的時程, 我們提出了一個架構於four-quadrant類比乘法器的數位混波器。 從模擬結果上我們可以得到其功率轉換增益約為-12dB, $P_{1dB}$點約為-0.2dBm, $IIP_3$約為7dBm, 而功率消耗則為4mW。我們亦利用TSMC CMOS $0.35\mu m$ digital的製程技術實現此電路, 並且作了測試驗證。我們將模擬與測試之結果作了比較並且有一深入的分析。最後, 我們利用以上的理論分析, 配合此一數位式混波器, 歸納出此混波器的設計準則。

Requests of wireless communication push the researches of front-end modules. The mixer is an important element of the front-end. In this thesis, we address our discussions at the noise and linearity analysis for the current commutating mixer, choosing the CMOS Gilbert cell as the analysis target. A simple mathematical and physical model, which indicates the elationship between the noise and linearity performance and the design arameters, such as the device dimension and biasing, is roposed to perform the analysis. Through the model, an instant prediction of the (noise/linearity) performance of the Gilbert cell mixers can be achieved. A comparison between the evaluation of the derivation result and the simulation result is also taken and a sufficient match is shown. Trade-off exists among all the figure-of-merits of the current-commutating mixer. A rough theoretical derivation is done and the simulation is taken to verify it. To shorten the design time and improve the portability, a digital mixer based on the architecture of the four-quadrant multiplier is also proposed in this thesis. The simulation results showed an adequate performance with the conversion gain of -12dB, $P_{1dB}$ of -0.2dBm, $IIP_3$ of 7dBm and power dissipation of about 4mW. The circuit is also fabricated in TSMC $0.35\mu m$ 1P4M standard CMOS process and though there's a quite large gap between the measurement and simulation esult, a reasonable reason is concluded to explain these problems. Exploiting the theoretical derivation previously and the proposed circuit, a general design guideline for the digital mixer is concluded. A conclusion and feasibility are provided finally.