具雙載子接面電晶體式矽視網膜結構之新型互補式金氧半矽視網膜影像感測系統以及八位元低功率類比至數位轉換器設計

Abstract

在本篇論文中，一個具雙載子接面電晶體式矽視網膜結構之新型互補式金氧半矽視網膜影像感測系統用來實現視網膜被提出並且分析。在新的互補式金氧半矽視網膜影像感測器中，每個像素包含了一個在標準金氧半製成中的雜散 PNP 雙載子電晶體，兩個用來實現視網膜中水平細胞工作在臨界區域之N通道金氧半電晶體，一個用來當選擇器的P通道金氧半電晶體，以及另一個P通道金氧半電晶體，其功能是給沒被選到的像素一個適當的電壓。兩個N通道金氧半電晶體的閘極被接到一個固定電壓源，藉由調整此電壓，影像平坦的範圍可被調整。在台積電零點二五微米製成中用P井當基極以及用深N井當集極的雜散NPN接面電晶體被用來實現視網膜中的光接收細胞 。 藉由連接NPN以及PNP之射極，視網膜中的雙載子細胞可被輕易的實現。為了要讀出像素中的訊號，我們使用了差動雙重取樣電路使得在讀出時獲得最高的訊號雜訊比。而由於雙載子細胞可被此矽視網膜實現，我們可透過此矽視網膜影像感測系統去擷取影像的邊緣。因此，原有的影像的邊緣可被增強。此外，由於視網膜中的光接受細胞，水平細胞以及雙載子細胞都在像素中被實現。此種架構的矽視網膜更時應用超大型積體電路的實現。此32 x 32 矽視網膜經由HSPICE模擬驗證無誤。每個像素的面積為20 um x 20um而填滿比率為50%。整個晶片面積為1300 um x 1300 um。整個晶片耗電量在3.3V時為30mW。 八位元，操作頻率為20 M sapmle/s的低功率類至數位轉換器是根據多步驟管線流的架構。每一級的解析度為1.5 bit且具有數位錯誤更正演算法。全差動的架構被用來減少共模雜訊以及二項諧和失真。由於低功率的考量，比較器以及類比至數位次轉換器並不消耗DC功率。此外，我們採用了低功率望遠鏡式運算放大器來用在乘法數位至類比轉換器中。使用零點二五微米製成，八位元類比至數位轉換器經由模擬驗證無誤。晶片面積為1000 um x 1200 um。類比部分的功率不包含偏壓電路為18mW。數位部分不包含緩衝器則為3mW。

In this thesis, a new CMOS retinal imager with BJT-based silicon retina structure is proposed and analyzed to implement the function of the vertebrate retina. In the new structure of CMOS retinal imager, each pixel consists of one parasitic PNP bipolar junction transistor (BJT) in the standard CMOS process, one parasitic NPN BJT with deep N-well as collector, two N-type MOSFETs in subthreshold region are used to implement the function of the horizontal cell in the vertebrate retina, one select P-type MOSFET, and one PMOS transistor to provide suitable bias for the deselected pixel. The gates of the two N-type MOSFETs are connected to a constant voltage source. By tuning the voltage, the smoothing range of the image can be tunable. The parasitic NPN bipolar junction transistor with P-well as base and deep N-well as collector in TSMC 0.25um CMOS process is used in each pixel to implement the function of photoreceptor cell in the vertebrate retina. By connecting both emitters of NPN and PNP bipolar junction transistors together, the function of the bipolar cell in the human eye can be easily realized. To readout the pixel signal, the double differential sampling (DDS) readout circuit is used and the signals can be readout with larger signal-to-noise (SNR) ratio. Due to the bipolar cell can be performed, the edge of image pattern can be extracted through the proposed CMOS retinal imager system. Thus, the edge of original image pattern is enhanced. Beside, since the photoreceptor cell, horizontal cell, and bipolar cell are all implemented in each pixel, the proposed is more suitable for VLSI implementations. The correct operation of this 32x32 CMOS retinal imager has been verified through HSPICE simulations. By using the new proposed structure, an experimental 32x32 CMOS retinal imager chip has been fabricated by using 0.25um CMOS technology. The pixel area of this sensor is 20um x 20um and the fill factor is 49%. Total chip area is 1300 um x 1300 um. The chip has the power dissipation of 30mW at 3.3V. The structure of 8-bit, 20 Msample/s low power analog-to-digital converter is based on the mutistep-pipelined structure. The resolution of each stage is 1.5 bit with digital error correction. Fully differential structure is used to reduce second-order harmonic distortion and common-mode noise. For low power consideration, both comparator and analog-to-digital subconverter (ADSC) has zero dc power dissipation. Also the low-power telescopic opamp is used in the multiplying digital-to-analog converter (MDAC). Using 0.25um CMOS process, the correctness of the designed ADC is verified by HSPICE simulation results. The active area of this chip is 1000um x 1200 um. The power dissipation of analog parts without biasing circuit of opamp is 18mW, and the digital part without output buffer is 3 mW at 3.3V.