用於JPEG 2000的Embedded Block Coding之硬體架構設計

Abstract

JPEG 2000 Part 1這分新的標準採用了新穎的影像壓縮技術，因而擁有眾多特點是以往標準所無法達成的。然而JPEG 2000中的embedded block coding這個演算法用到大量的bit-level運算，使得JPEG 2000在一般用途的中央處理器上執行時並不是很有效率。解決的辦法之一便是透過ASIC的設計。 本篇論文之目的即是要替JPEG 2000中的embedded block coding設計一個特定的硬體架構。我們修正embedded block coding的演算法，從而提出了memory-saving的演算法來減低記憶體需求量。這個memory-saving的演算法可以省去4K bits的記憶體。 為了加快運算速度，我們討論了embedded block coding中四種不同的平行度。最後在我們的晶片中採用了pixel-skipping的方法來利用pixel-level的平行度。在MQ Coder的設計中，除了利用管線化的架構來加快MQ Code的運算速度之外，我們並提出了variable-cycle code-register renormalization與multi-cycle flush的方法。透過這二個方法，我們可大幅提升MQ Coder的時脈，在post-layout simulation中可達到142 MHz。 我們將我們所提出的方法與架構實做成晶片。此晶片的面積為3.345x3.313mm2。在post-layout simulation時，其時脈可達至142 MHz，而我們預期在製做完成後的工作頻率是100 MHz。當它工作在100 MHz時，大約花503.42 ms的時間來壓縮三十張256x256、4:4:4格式的彩色影像。或者是花0.92秒來完成三十張512x512、4:2:0格式的彩色影像。因此，此晶片可支援未來一些受歡迎的應用，如Motion JPEG 2000。

The current state of JPEG 2000 Part 1 is International Standard. It adopts the novel image compression techniques and provides the richest set of features that are not served by current standards. However, the bit-level computations of the embedded block coding operations make JPEG 2000 hard to be efficiently executed on the general-purpose CPU architectures. One of the viable solutions is through an ASIC design. The objective of this thesis is to design a dedicated hardware for the embedded block coding algorithm in JPEG 2000. In order to reduce the memory requirement problem of the embedded block coding algorithm, we propose the novel memory-saving algorithm, which can achieve 20% reduction in on-chip memory. Four different levels of parallelisms in block coding algorithm are described, and we use the pixel-skipping method to exploit the pixel-level parallelism for accelerating the encoding time. Besides, we propose the variable-cycle code register renormalization method and multi-cycles FLUSH procedure in our pipelined MQ Coder architecture, such that the clock rate can be enhanced up to 142MHz (at post-layout simulation). Based on the methods we proposed and adopted, the prototyping chip is implemented with the area 3.345x3.313 mm2. We expect the chip can run at 100 MHz although it achieves 142 MHz clock rate at post-layout simulation. With the expected frequency (100MHz), it takes about 503.42 ms to encode 30 frames with 4:4:4 format, 256x256 images or about 0.92 s to encode 30 frames with 4:2:0 format, 512x512 images. Therefore, it can support some popular applications such as the forthcoming Motion JPEG 2000.