250百萬位元數位傳輸系統設計

Abstract

本論文描述1000Base-T以太網路的收發器的初步設計，也就是單一通道上的單向數位傳輸系統設計。其設計內容包括了建立一組正確且適合系統模擬的通道模型，以及設計接收端各部主要電路的架構，在提出設計上的考量並逐步設定各項參數後，以Matlab模擬驗證電路架構的可行性以及性能表現。 在進行系統模擬驗證時，實際通道的特性必須被完整地模擬出來。除了對實際通道進行量測與做必要的數據處理外，為了節省模擬通道所需要的電腦運算時間，通道模型將以20階以內的轉移函數方式呈現，可大幅減少運算需求. 為了降低系統實現的成本，同時兼顧良好的性能，本論文將對系統中最龐大的部分—數位等化器進行最佳化。內容包括了對數位等化器的適應性特性做探討與解讀，並依此決定為等化器的可行方向與預測其行為。另外也因應數位等化器的功能配置給予良好的初始設定，使等化器可以快速完成適應性追蹤，並準確地落在最佳配置點上。 本設計經過模擬驗證，除了有良好的系統穩定性外，在未對信號解碼偵錯的情況下，性能也已能符合IEEE 802.3ab的測試標準。

This thesis describes a preliminary design for 1000Base-T ethernet transceiver, a unilateral digital transmission system over a unit channel. This thesis first introduces a precise channel model which is good forsimulation on computer, and then discusses the detail architectures of main blocks of receiver. After deciding architectures and all of their parameters with design consideration, a series of simulations with Matlab will be made to verify this design. The practical channel characteristics should be properly simulated in system simulation. The channel model provided in this thesis is not only the results of measurement, but also in a simple form of transfer function so that the simulation time of channel will be short on computer. To reduce the cost of system implementation and keep good performance at the same time, this thesis will try to optimize the digital equalizer, the most enormous part of the system. This thesis will first discuss the characteristics and behavior of adaptive equalizer and then try to slim the size down. By refering to the functions of each part of equalizer this thesiswill propose a set of initial parameters for equalizer. With these initial parameters, the equalizer will finish the adaption in several thousands of symbol period and settle down in the optimia situation well. By simulation, the design proposed in this thesis is verified that it has good stability and meets the performance requirement of IEEE 802.3ab, although the error correction coding scheme is absent.