Gigabit Ethernet 網路接收機中管線化決策迴授等化器之ASIC設計

Abstract

本論文中，主要探討新一代以雙絞線為傳輸界質的Gigabit Ethernet 1000 Base-T之通道等化器之設計；由於Gigabit Ethernet 1000 Base-T使用了Trellis coding modulation (TCM)，因此，一般常用之Decision feedback equalizer不能有效的使用，我們比較各種Equalizer與TCM Decoder結合的可行性，經由計算機的模擬發現，Decision Feedback Sequence Estimation (DFSE) 能得到一最符合要求的結果，然而DFSE之計算複雜度會隨著通道響應長度而呈指數的增加，為了克服此問題，我們使用了partial DFE以縮短通道響應並配合一些近似以進一步簡化硬體實現所需的硬體複雜度。而在Partial DFE 的設計上，為了符合高速運算的要求，我們透過延遲係數更新的方式來對其做Pipelining的動作，且以VHDL硬體描述語言加以實現。

This thesis consider the equalization design for the new generation Ethernet 1000 Base-T, the Gigabit Ethernet over twisted-pair. Due to the use of the Trellis Coded Modulation in Gigabit Ethernet 1000 Base-T, the direct application of the decision feedback equalizer (DFE) can't perform effectively. In the thesis, we study the equalization methods for the TCM coded signal. We found that the decision feedback sequence estimation (DFSE) can have satisfactory performance. However, the computational complexity of the DFSE grows exponentially with the channel response length. To solve the problem, we use the partial DFE to shorten the channel response. This method can effectively reduce the hardware complexity. As to the design of the partial DFE, we use a pipelined delayed least mean square (LMS) DFE to meet the high-speed requirement of the Gigabit Ethernet. Finally, we implement the DFE using the VHDL hardware description language.