Gigabit Ethernet網路接收機中 TCM解碼器之ASIC設計

Abstract

本論文主要探討Gigabit Ethernet (1000 Base-T) 中TCM decoder 之電路設計。這裡所用的解碼方式是大家所熟知的維特比演算法。在維特比解碼器的硬體架構中，survivor memory unit (SMU) 是一個必要的單元。用在1000 Base-T Viterbi decoder 的SMU 通常是使用register-exchage method (REM)，但是此種方法會使用較大的面積及較複雜的接線。在本論文中，我們採用了一種稱為register-trace-back (RTB)的新架構來代替REM ，這可以有效的節省電路的面積及簡化接線的複雜性。最後，我們將此解碼器用VHDL 硬體描述語言來加以實現。

This thesis considers the trellis coded modulation (TCM) decoder design for the Gigabit Ethernet (1000 Base-T transceiver. The decoding scheme involves the well-known Viterbi algorithm. In the hardware implementation of the Viterbi decoder, an important module is called survivor memory unit (SMU). Conventionally, the SMU of the 1000 Base-T Viterbi decoder is implemented using the register-exchage method (REM) which results in a large area and complex routing. In this thesis, we employ a new method called the register-trace-back (RTB) structure for ASIC design of TCM decoder. This method can effectively reduce the area and simplify the routing. Finally, the overall decoder design is realized using the VHDL hardware description language.