標題: | 第三代耙狀接收機之低功率設計與DSP實現 Low-power Design of 3G Rake Receiver & Its DSP Realization |
作者: | 郭顯豐 Hsien-Feng Kuo 陳紹基 Dr. Sau-Gee Chen 電子研究所 |
關鍵字: | 耙狀接收機;數位訊號處理器;通道估測;低功率設計;相關器;Rake receiver;DSP;channel estimation;low-power design;correlator;WCDMA;LMMSE |
公開日期: | 2000 |
摘要: | 本論文提出第三代行動通訊(寬頻分碼多工存取)系統中耙狀接收機之數位訊號處理器的實現與低功率的設計,包含傳統耙狀接收機、適應性最小均方差耙狀接收機、線性內插通道估測與滑動窗型通道估測之定點及浮點、執行效能、錯誤率與運算複雜度的比較。另外由於低功率設計對於可攜式應用是愈來愈重要的,我們亦提出了一些低功率相關器的設計,並比較了不同速度與電壓之下各種相關器的功率消耗。 In this thesis, the DSP realization and low-power design of the Rake receiver in the third Generation Mobil Communication (Wideband Code Division Multiple Access) systems were presented. The conventional Rake receiver and adaptive LMMSE Rake receiver with channel estimation of linear interpolation and sliding window were realized, with fixed-point and floating-point operations. Their performances are compared, including BER and computational complexities. Since low-power design is critical for portable applications, some new low-power correlators were proposed. We compared the power consumption of different correlators in different speeds and voltages. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT890428058 http://hdl.handle.net/11536/67132 |
顯示於類別: | 畢業論文 |