運動輪廓硬體化之改善

Abstract

在運動控制中，適當的加減速規劃可使機構運動更加的平滑，以避免系統因為速度急遽的變化而產生過大的振動。基於此，本論文著眼於加減速曲線規劃之研究，除了傳統已經發展的梯形、S型加減速曲線外，更提出符合系統響應之指數型加減速曲線，並藉由已發展之插值法則，進一步分析運動控制系統中不同加減速曲線之圓弧徑向誤差。此外，根據所提出之加減速規劃方法，利用場效可規劃邏輯陣列(FPGA)晶片及Verilog硬體描述語言來實現一運動控制電路。硬體實現採用階層式與模組化的方式，將各功能模組獨立設計驗證，來簡化電路設計與模擬驗證的過程，並利用一包含混和型步進馬達、微步進驅動器、FPGA運動控制電路及人機介面所組成之開迴路運動控制系統，來評估所提出的加減速規劃法則之效能。

In motion control, acceleration/deceleration techniques are indispensable for the smooth motion without vibration at the transient state. Thus, in this thesis, an approach for generating acceleration/deceleration curves including the conventional motion profile of linear and s-shape, as well as the improved exponential motion profile, is proposed. Based on the acceleration/deceleration and interpolation algorithm, the path error is analyzed for linear, s-curve and exponential curves in case of circular interpolation to evaluate the performance of motion control systems. Furthermore, a motion control circuit based on the calculation algorithm is designed by the Verilog hardware description language (HDL) and implemented in FPGA provided by ALTERA. To simplify the circuit design and simulation verification, each function element is modular and independently tested so that the entire system can be created by connecting blocks up. In addition the motion control circuits, we make use of the open-loop motion control system consisting of the GUI of Human-Machine Interaction, a FPGA-based motion controller, the micro-step driver, and the hybrid stepper motor to evaluate the performance of acceleration/deceleration algorithm.