超薄閘極氧化層退化機制之完整研究

Abstract

加壓在高電場的薄閘極氧化層退化現象對金氧半元件可靠性是非常重要議題。隨著互補金氧半技術微小化至深次微米，想要以物理瞭解氧化層退化機制是相當迫切地。因此，這論文主要目的是去研究薄閘極氧化層至超薄閘極氧化層經由高電場加壓之退化機制。 首先，去評估經由F-N加壓所產生在氧化層內填滿的陷阱是非常重要的。第二章節是利用一個靈敏的閘極二極體技術去評估在氧化層內填滿的陷阱，並已經展示這順向閘極二極體技術能夠發現應用在評估金氧半場效電晶體氧化層內填滿的陷阱。在填滿陷阱密度與電子加壓通量之間，相關於順向電流頂點的閘極電壓平移量測產生一個次方定理的關係。然後，此次方定理的關係式對研究 SILC 以及介電質崩潰扮演一個重要角色。最近實驗性展示建議非彈性陷阱-輔助-穿隧 (ITAT) 當作加壓引致漏電流 (SILC) 的原因，並且一連串模型已被發表。因此，第三章節提出一個藉由數值計算相當可理解的過程去驗證非彈性陷阱-輔助-穿隧 (ITAT) 當作SILC的機制。這過程主要是包含SILC到氧化層崩潰去平衡模型與實驗兩者。這物理機制方面被釐清如下：(i) ITAT贊同在特定位置有最大穿隧進入陷阱與離開陷阱的可能性；(ii)總共產生電中性陷阱密度之被佔據部分是非常低，已確保ITAT的可能性。 其次，對於氧化層厚度小於5nm去研究軟崩潰與硬崩潰這兩者的原因是相當迫切地。第四章節已展示一個氧化層變薄滲透模型能夠重現在3.3nm氧化層厚度的時間對軟崩潰統計分佈。基於上述分析，軟崩潰與硬崩潰的原因能夠被釐清如下：(i) 軟崩潰機制本質上屬於硬崩潰，換句話說，它們分享產生相同電中性陷阱的過程與遵循波乙生隨機統計分佈；(ii)這兩者崩潰是獨立事件，對應於有不同剩餘氧化層厚度的需求；(iii) 硬崩潰發生地方是不同於第一次發生軟崩潰地方。緊接著，在第五章節描述由電性決定軟崩潰與硬崩潰路徑的位置，並且對遭遇軟崩潰時也提供一個n型通道金氧半場效電晶體的低頻雜訊Sid深入分析。在軟崩潰之後，Sid 起源於軟崩潰滲透路徑經由底下通道串連能夠非直接耦合至汲極的電流擾動，或是形成軟崩潰滲透路徑接近汲極就能直接耦合至汲極的電流擾動。特別地，在整個軟崩潰其間Sid的擾動是第一次被觀察到。因為關於在軟崩潰路徑被捕捉-被釋放的過程，它真正地驗證動態滲透的原因，這現象是非常顯著地。 最後，為了提供一個氧化層退化機制進一步分析，一個在矽材料衝擊游離化的量子效益量測能夠實質上評估電子注入整個閘極氧化層的平均能量。第六章節展示量子效益實驗已被完成在一個0.13um n型通道金氧半場效電晶體上。在閘極到汲極與閘極到源極重疊區域衝擊游離化產生電洞主控基極電流已被發現，並且它被閘極電流除以就是為邊界量子效益 (EQY)，這邊界量子效益與已存在的理論相當符合。更進一步量測顯示 (i)在加壓引致漏電流 (SILC) 的注入電子屬於非彈性行為；並且 (ii)這注入電子在軟崩潰時比在SILC時，遭遇到更多能量損失或是能障更低。

Degradation phenomena of thin gate oxides exposed to high field stress are a very important issue concerning the reliability of MOS devices. The desire for a physical understanding of the oxide degradation mechanisms is quite urgent as CMOS technology is scaled into the deep submicron regime. Thus, the main purpose of the dissertation is to investigate the degradation mechanisms of thin to ultrathin gate oxides during the high field stressing. Firstly, it is very important to estimate in advance the filled traps generated inside the oxide during F-N stressing. Chapter 2 is to exploit a sensitive gated-diode technique to assess the filled traps inside the oxide. It has been demonstrated that the forward gated-diode technique can find its potential applications in assessing the filled traps in MOSFET thin oxides. Our measurement of the gate voltage shift associated with the forward current peak produces a power law relation between the filled trap density and the electron stress fluence. Then, the power law relation plays an important role in the study of SILC and dielectric breakdown. Recent experimental demonstrations suggest inelastic trap-assisted tunneling (ITAT) as the origin of stress-induced leakage current (SILC) in oxide films, and a series of models are published. Thus, Chapter 3 presents a quite comprehensive procedure to verify inelastic trap-assisted tunneling (ITAT) as SILC mechanism. This procedure is mainly to balance both model and experiments covering SILC until oxides breaks down. The physical aspects of SILC mechanism are clarified in the followings: (i) ITAT does favor the maximum likelihood of tunneling to and from the traps at the specific position; and (ii) the occupied fraction of the total generated neutral density is very low ensuring the possibility of ITAT. Secondly, it is very urgent for the oxide thickness less than 5nm to study the origins of dielectric breakdown including both soft and hard breakdown. Chapter 4 has demonstrated that an oxide thinning cell-based percolation model with parameter correlation can reproduce the statistical distributions of time to soft breakdown in 3.3nm thick oxide. According to the above analysis, the origins of soft and hard breakdown can be clarified in the followings: (i) soft breakdown behaves intrinsically as hard breakdown, that is, they share the same defect (neutral trap) generation process and follow Poisson random statistics; (ii) both are independent events corresponding to different residual oxide thickness tox’ requirements; and (iii) hard breakdown takes place in certain path located different from that for the first soft breakdown. Subsequently, the localization of SBD and HBD paths has been determined electrically, as stated in Chapter 5. Chapter 5 also provides an in-depth analysis on the low-frequency noise (Sid) of nMOSFETs undergoing soft breakdown. The post-SBD Sid does originate from current fluctuations in the SBD percolation paths, which can couple indirectly to drain via underlying channel in series, or directly to drain if SBD path is formed close to drain extension. In particular, a fluctuation in Sid itself in the whole SBD duration is observed for the first time. This phenomenon is very striking since it indeed evidences the dynamic percolation origin concerning the trapping-detrapping processes in and around the SBD paths. Finally, in order to provide a further analysis of the oxide degradation mechanisms, a measure of quantum yield of impact ionization in silicon can essentially assess the average energy of electrons injected into the almost whole gate oxide. Chapter 6 shows quantum yield experiment performed on a 0.13-um nMOSFETs. It is found that the impact ionization induced holes in the gate-to-drain/source overlap regions dominate the substrate current, and as divided by the gate current, the resultant Edge Quantum Yield (EQY) quite matches the existing theory. Further measurements reveal that (i) the injected electrons in stress-induced leakage current (SILC) mode feature inelastic behavior; and (ii) in soft breakdown the injected electrons experience more energy loss or barrier lowering than SILC.