磊晶互補式金氧半鎖定物理模型及晶片靜電放電保護

Abstract

本篇論文包括對磊晶互補式金氧半(CMOS)中的鎖定物理模型及互補式金氧半積體電路輸入/輸出的靜電保護電路放電模型加以深入研究，首先，對P-N-P-N結構鎖定物理的解析模型深入了解與研究，剖解磊晶互補式金氧半中寄生的P-N-P-N結構所形成之矽控整流器(SCR)固有特性，歸納鎖定效應時的維持電壓與電流相互物理機制之簡潔公式及設計準則。其次，探討閘極接地N型金氧半（NMOS）場效電晶體結構之靜電放電保護電路相關參數的模型，以觀察各參數在不同磊晶層的變化模型，最後，整合前述兩種結構，設計出低電壓觸發矽控整流器(LVTSCR)靜電保護電路。將積體電路中互補式金氧半寄生的P-N-P-N結構之鎖定效應的缺點，藉由低觸發閘極接地N型金氧半場效電晶體結構；強化電路設計成輸入/輸出的靜電保護技術中的優點，同時加以深入探討分析這些結構之內部物理行為。

Latchup phenomenon of CMOS devices is a very critical issue from the standpoint of the reliability concern. The physical behaviors of the latchup mechanisms were investigated from the time the CMOS technology was invented and considered as a major research subject while being continually scaled into the deep submicron. Thus, the first part of the dissertation is to dig out the physical holding voltage model involving latchup mechanisms of the epitaxial CMOS devices. The unavoidable Electrostatic Discharge (ESD) damage for the semiconductor devices in the system is the other reliability issue. A lot of on-chip ESD protection circuits have been designed to keep the internal core circuit from destroying by ESD energy. Therefore, the second part of the dissertation is dedicated to the two ESD protection circuits in terms of the grounded-gate NMOS and the Low Voltage Triggering SCR (LVTSCR).