使用多重氧化層技術成長之雙閘極金氧半元件偏壓與溫度效應之可靠性研究

Abstract

系統整合晶片在未來的雙閘極金氧半元件技術中已受到廣泛的注意。這其中關鍵的技術在於如何在同片晶圓中成長不同的氧化層厚度以使用不同的操作偏壓。為了使電路得到最佳化的性能，不論電路的架構和可靠性問題都必須在整合所有電路區塊時加以考慮。然而，隨著高度的積體化與功率散逸的增加，僅考慮在室溫環境下之熱載子可靠性來預測元件生命期是不足夠的。溫度效應將突顯出其重要性。另一方面，熱載子效應(Hot Carrier Effect)在P型金氧半元件中本較為微弱，負偏壓溫度效應(Negative Bias Temperature Instability, NBTI)將隨著更高的操作溫度與更低的操作偏壓而被突顯出來。 在本研究論文中，我們首先探討七種加壓測試情形偏壓與溫度效應的可靠性。本實驗所使用的測試元件包括兩種不同世代的元件，分別為0.35微米通道長度配合65埃的氧化層厚度與0.18微米通道長度配合32埃的氧化層厚度，且使用多重氧化層技術所製造。對於N型金氧半元件，0.35微米元件生命期將決定於加壓測試在最大基極電流的狀態及室溫環境下; 0.18微米元件生命期將決定於加壓測試在閘極電壓等於汲極電壓的狀態及高溫環境下。而不同於N型金氧半元件，不論0.35微米或0.18微米之P型金氧半元件的元件生命期決定於加壓測試條件為閘極電壓等於汲極電壓的狀態及高溫環境下。根據實驗分析顯示，我們提出一個新的機制，即是熱載子效應與負偏壓溫效應並非完全獨立，會有高能量電洞增強負偏壓溫度效應(NBTI)傷害的情況發生。因此，此一機制對於未來P型金氧半元件之可靠性測試將突顯其重要性。

System-on-a-chip (SoC) has received considerable attention for the future dual gate CMOS technology. One of the major technological requirements of SoC is the ability to grow multi-gate oxide thickness, and then multiple supply voltages are used on one chip. To optimize the circuit performance, both circuit architecture and reliability are merged for the design consideration of integration. However, with high density of integrated circuits and an increase of power dissipation, the lifetime prediction is not sufficient by considering only the hot carrier reliability at room temperature for SoC. The temperature effect is of cirtical importance. Although the hot carrier (HC) effect is weak in PMOSFET, negative bias temperature instability (NBTI) is more pronounced at higher operation temperature and a lower operation voltage. In this thesis, we investigated the bias and temperature dependent reliability for the SoC with 7 kinds of stress conditions. This SoC includes two generation of devices with 0.35µm gate length, 65Å gate oxide and 0.18µm gate length, 32Å gate oxide. They were fabricated using multi-oxide technology. For NMOSFET, the stress at IB,MAX and room temperature dominates the device lifetime for 0.35µm devices, while the stress at VG=VD and high temperature dominates the device lifetime for 0.18µm devices. In contrast, the stress at VG=VD and high temperature was shown to dominate the device lifetime for both 0.18µm and 0.35µm PMOSFET in SoC. In particular, for the first time, a new mechanism called enhanced NBTI effect has been proposed. Experimental results show that in addition to the HC effect and NBTI in PMOSFET, we have seen an enhanced degradation caused by the energetic holes in PMOSFET. Therefore, this is a very important factor for reliability test of PMOSFET’s.