寬頻分碼多重進接犁耙接收器之FPGA實現及實驗研究

Abstract

為了實現第三代無線行動通訊，使用結合了許多先進技術的寬頻分碼多重進接(W-CDMA)系統是必然的趨勢。另一方面，FPGA (Field Programmable Gate Array)是一種可規劃邏輯陣列IC，使用者可以隨意規劃任意邏輯電路，並且可直接在FPGA IC上驗證設計電路。本論文之主題為探討寬頻分碼多重進接系統基頻接收器數位設計實現的可行性。在本篇論文中，吾人以數位電路實現寬頻分碼多重進接系統基頻接收系統，結合犁耙接收器(RAKE receiver)、通道估計(channel estimation)、傳送功率控制(transmit power control)、自動頻率控制(automatic frequency control)等。此接收機可以搜尋三個不同的路徑並同時解調，並且針對頻率偏移做有效估測。最後吾人提出一種數位的方法解決時脈恢復(clock recovery)的問題。論文中的電路設計是以VHDL描述並以Xilinx FPGA實現為目標。

To realize the third-generation mobile communication systems, known as International Mobile Telecommunications-2000 (IMT-2000), the wideband CDMA (W-CDMA) schemes incorporating as many recent technology developments as possible is necessary. On the other hand, FPGA (Field Programmable Gate Array) is a programmable combinational logic IC. The user can design any logic circuit and verify the design on the FPGA IC directly. In this thesis, we investigate the feasibility of digital design of a W-CDMA baseband receiver. In particular, a digital circuit is used to realize the receiver. The circuit includes RAKE receiver, channel estimation, transmit power control and automatic frequency control, etc. The receiver consists of a searcher with three-finger combiner, and each finger can perform demodulation for three dedicated physical channels simultaneously. It can also provide effective estimation of frequency offsets. Finally, we propose a new digital method to solve the clock recovery problem in the proposed circuit. The circuit in the thesis is described by VHDL language and targeted for Xilinx FPGA implementation.