射頻電路與高速輸入輸出界面電路之靜電放電防護設計

Abstract

隨著近年來通訊技術與積體電路製程的持續演進，無線與有線通訊裝置已經成為生活中不可或缺的重要設備。藉由無線通訊傳輸資料，使用者可更機動地收發各種訊息，此演進大幅提昇了資料傳輸的方便性。有線傳輸技術的發展，加速無線接取點與伺服器間的資料傳輸速度。積體電路製程技術的發展，降低了無線與有線通訊裝置的製造成本，更激起使用者對通訊裝置的需求與使用意願。 所有電子產品，包含積體電路產品，必須於量產時符合可靠度的規範，以便讓使用者用得安心，並提供該產品足夠的耐用年限。靜電放電(Electrostatic Discharge, ESD)是積體電路可靠度中最重要的一環，大多數電子產品的故障與損壞均與遭受靜電放電轟擊有關。為對積體電路提供有效的靜電放電防護，所有積體電路與外界接觸的銲墊(Pad)皆須搭配靜電放電防護設計，包含電源銲墊與輸入輸出銲墊，而輸入輸出銲墊上的靜電放電防護電路會在訊號路徑上產生寄生效應。無線通訊裝置中的射頻(Radio- Frequency, RF)前端電路，亦需要搭配靜電放電防護設計，因為他們連接射頻收發機與外接之濾波器或天線。由於射頻電路的工作頻段高達數GHz至數十GHz，如此高頻的工作頻率對於訊號路徑上的寄生效應有極嚴格的限制，若訊號路徑上的寄生效應過大，將導致射頻電路性能的嚴重衰減。除了無線通訊之前端電路，有線傳輸系統中的前端電路，近年來也在新型傳輸標準中提昇其傳輸速率，故有線傳輸系統中的輸入輸出界面電路對訊號路徑上的寄生效應要求也日趨嚴格。以上情況引發射頻電路與高速輸入輸出界面電路之靜電放電防護設計的挑戰：如何在最低程度性能衰減的前提下達成最高的靜電放電耐受度，亦即如何將靜電放電防護元件的寄生效應最小化。 除此之外，互補式金氧半製程的演進，更進一步提昇靜電放電防護設計的困難度。對核心電路性能而言，使用先進的積體電路製程，電晶體的工作頻率可以提昇，並可降低元件的雜訊、功率損耗。隨著積體電路製程的進步，電晶體的元件尺寸可以大幅微縮，故可整合更多電路功能於單一晶片內，此舉開啟了系統單晶片(System on Chip, SoC)的應用。然而靜電放電轟擊的強度並未隨著積體電路元件微縮而降低，隨著積體電路製程的演進，電晶體閘極氧化層的崩潰電壓逐漸降低，使電晶體愈容易遭受靜電放電轟擊而損壞，因此另一個挑戰隨之產生：如何在先進製程中降低靜電放電轟擊時於靜電放電防護元件上產生的跨壓，以有效保護內部電路。上述兩個挑戰為本論文的研究動機，本論文由積體電路周圍的銲墊設計開始，循序漸進至積體電路內部的全晶片靜電放電防護設計與射頻前端電路設計；由單一晶片的電路設計，延伸至整個電子系統的電路板層級元件充電模式(Board-Level Charged Device Model)靜電放電防護探討。本論文的研究方向包括：(1)分析目前已發表的射頻電路與高速輸入輸出界面電路之靜電放電防護設計相關文獻、(2)超低寄生電容的銲墊設計、(3)寬頻分散式放大器之靜電放電防護設計、(4)搭配全晶片靜電放電防護設計之差動式低雜訊放大器(Low-Noise Amplifier, LNA)、(5)高速輸入輸出界面電路之靜電放電防護設計、(6)電路板層級元件充電模式靜電放電(Board-Level Charged-Device-Model ESD)對積體電路產品之影響。 本論文第二章針對目前已發表的射頻電路與高速輸入輸出界面電路之靜電放電防護設計進行分析，將各種設計分門別類，並歸納各種設計的優缺點與成效。本章首先以量測結果說明靜電放電防護元件的寄生效應，並闡述靜電放電防護元件對電路性能造成之負面影響。除寄生效應外，靜電放電防護元件於積體電路遭受靜電放電轟擊時的元件特性亦相當重要，因為這關係該積體電路的靜電放電耐受度。本章將目前已發表的射頻電路與高速輸入輸出界面電路之靜電放電防護設計分為三種方式，第一種為使用電路技巧降低靜電放電防護元件寄生效應的設計方式，使用電路技巧，可將靜電放電防護元件的寄生效應透過阻抗匹配或阻抗隔絕的方式大幅降低，但額外的元件可能提高晶片面積或製作成本。第二種方式藉由改變元件佈局以降低靜電放電防護元件的寄生效應，雖然寄生效應的改善幅度較使用電路技巧的方式小，但由於不需外加元件，故晶片面積與製作成本亦小於使用電路技巧的方式。第三種方式藉由改變製程降低靜電放電防護元件的寄生效應，改變半導體的摻雜濃度，可改變接面的寄生電容值，此法雖可以最直觀的方式降低靜電放電防護元件的寄生效應，但改變製程的可能性在一般應用中並不常見。本章後段比較各種設計的複雜度、改善後之寄生效應、靜電放電耐受度、與面積使用效率。 除了靜電放電防護元件以外，銲墊也會在訊號路徑上對射頻訊號造成負面影響，為了提昇射頻電路之性能，銲墊的寄生電容值也必須盡量降低。本論文第三章提出一種新型具有超低電容值的銲墊架構，可於一般互補式金氧半製程中實現，不需修改製程。在此新型銲墊架構中藉由使用電感，可抵銷銲墊本身的寄生電容值，以大幅降低整個銲墊的等效寄生電容值。本研究於130奈米互補式金氧半製程中實現三種新型設計，分別在傳統銲墊的區域中，以一層、三層、五層金屬實現三種電感，故此新型設計不需增加銲墊面積。藉由不同電感值，可產生不同共振頻率，也可達成不同程度的銲墊電容改善量。實驗結果顯示，藉由銲墊下方電感產生的共振效應，等效銲墊電容可於特定頻段內大幅降低。以五層金屬實現電感的銲墊架構，在4.3 GHz至4.8 GHz的頻段內，等效銲墊電容值可降低至接近0 fF。利用此新型銲墊架構，將可降低因傳統銲墊電容造成的訊號延遲與訊號損耗，進而提昇射頻電路性能。 本論文第四章提出新型分散式靜電放電防護架構，並將其應用於寬頻分散式放大器，且以0.25微米互補式金氧半製程實現。當所有靜電放電防護元件的總電容為300 fF時，搭配傳統等尺寸式分散式靜電放電防護架構的分散式放大器，其人體放電模式(Human Body Model, HBM)與機械放電模式(Machine Model, MM)靜電放電耐受度分別為5.5 kV與325 V，且於1 GHz至10 GHz的頻段內擁有4.7 ± 1 dB的增益；搭配新型遞減尺寸式分散式靜電放電防護架構的分散式放大器，人體放電模式與機械放電模式靜電放電耐受度可大幅提昇至8 kV與575 V，且於1 GHz至9.2 GHz的頻段內擁有4.9 ± 1.1 dB的增益。這兩種分散式靜電放電防護架構均可與分散式放大器共同設計，以達成符合要求的射頻性能與靜電放電耐受度。 除了搭配靜電放電防護設計的寬頻射頻前端電路外，本論文第五章提出窄頻射頻前端電路與靜電放電防護電路的共同設計。本章使用130奈米互補式金氧半製程設計一個工作於5 GHz的差動式低雜訊放大器，並將數種新型靜電放電防護架構應用至該差動式低雜訊放大器。本研究為目前相關研究中，率先探討差動式低雜訊放大器接點對接點(Pin to Pin)靜電放電耐受度的研究。所有差動式低雜訊放大器的功率消耗皆為10.3 mW。沒有搭配靜電放電防護設計的差動式低雜訊放大器，在5 GHz的功率增益與雜訊指數分別為16.2 dB與2.16 dB。本章亦實現傳統雙二極體(Double Diode)靜電放電防護架構的差動式低雜訊放大器，此設計於各輸入銲墊至電源線與接地線間分別放置靜電放電防護二極體，其人體放電模式與機械放電模式靜電放電耐受度分別為2.5 kV與200 V，在5 GHz的功率增益與雜訊指數分別為17.9 dB與2.43 dB。第一個新提出的靜電放電防護設計使用雙矽控整流器(Silicon-Controlled Rectifier, SCR)，此設計於各輸入銲墊至電源線與接地線間分別放置矽控整流器提供靜電放電防護功能，其人體放電模式與機械放電模式靜電放電耐受度分別為6.5 kV與500 V，搭配此設計的差動式低雜訊放大器在5 GHz的功率增益與雜訊指數分別為17.9 dB與2.54 dB。第二個新提出的靜電放電防護設計於兩個差動輸入銲墊間插入靜電放電匯流排(ESD Bus)，藉此於兩個差動輸入銲墊間提供有效的靜電放電路徑，其人體放電模式與機械放電模式靜電放電耐受度分別為3 kV與100 V，搭配此設計的差動式低雜訊放大器在5 GHz的功率增益與雜訊指數分別為18 dB與2.62 dB。第三個新提出的靜電放電防護設計於兩個差動輸入銲墊間使用交叉耦合(Cross Couple)的矽控整流器，除了可提供單一輸入銲墊至電源線與接地線的靜電放電防護外，更可在不增加元件的情況下，額外提供兩個差動輸入銲墊間的接點對接點模式靜電放電防護功能，其此設計的人體放電模式與機械放電模式靜電放電耐受度分別為1.5 kV與150 V，搭配此設計的差動式低雜訊放大器在5 GHz的功率增益與雜訊指數分別為19.2 dB與3.21 dB。另一個靜電放電防護設計搭配雙二極體與交叉耦合矽控整流器，可達成4 kV人體放電模式與300 V機械放電模式的靜電放電耐受度，搭配此設計的差動式低雜訊放大器在5 GHz的功率增益與雜訊指數分別為19.1 dB與3.05 dB。除了比較靜電放電耐受度外，搭配各種靜電放電防護設計的差動式低雜訊放大器之射頻性能，亦於第五章內比較與討論。 本論文第六章提出高速輸入輸出界面電路之靜電放電防護設計。首先量測在130奈米互補式金氧半製程中P型擴散區與N井接面(P+/N-well)及N型擴散區與P井接面(N+/P-well)兩種二極體在不同尺寸下的靜電放電耐受度與寄生電容值。為了確保能提供一般商用規範的2 kV人體放電模式靜電放電耐受度，靜電放電防護二極體需使用40微米以上的周長實現。接著利用仿製接收級電晶體(Dummy Receiver NMOS)架構，將電晶體的閘極連接至輸入銲墊，並將電晶體的汲極、源極、基底接地，搭配選定之靜電放電防護二極體尺寸與電源箝制靜電放電防護電路，可量測此仿製接收級電晶體的靜電放電耐受度。由於仿製接收級電晶體的連接方式近似於一般接收級內電晶體的連接方式，故可由仿製電晶體的靜電放電耐受度推估一般接收級的靜電放電耐受度。此靜電放電防護設計亦應用至2.5 GHz的高速接收級界面電路，在250 fF寄生電容的限制下，此靜電放電防護設計可達成3 kV的人體放電模式靜電放電耐受度。此外本論文第六章提出一種新型設計，將原本置於輸入銲墊與接地線間的N型擴散區與P井接面(N+/P-well)二極體置換為矽控整流器，藉由與電源箝制靜電放電防護電路共用靜電放電偵測電路，輸入輸出接點的寄生電容可有效降低，並可藉由使用矽控整流器提昇靜電放電耐受度。本研究將靜電放電防護元件與部分靜電放電偵測電路置於輸入銲墊下方，可節省晶片面積，並降低訊號路徑上的寄生電容值。 完成單一積體電路晶片的靜電放電防護設計後，每個晶片皆須安裝至電子產品的模組內並進行功能測試，此時可能引發電路板層級元件充電模式靜電放電，導致晶片損毀。本論文第七章探討電路板層級元件充電模式靜電放電對積體電路產品造成的威脅，首先簡介晶片層級與電路板層級元件充電模式靜電放電的成因，並說明數個積體電路晶片遭受電路板層級元件充電模式靜電放電損壞的實例。由於電路板層級元件充電模式靜電放電的電流峰值與電子模組中的電路板尺寸有密切關係，第七章第二部分量測不同電路板尺寸所產生的電路板層級元件充電模式靜電放電電流波形，實驗結果顯示較大的電路板尺寸或將電路板充電至較高電壓，將導致較大的電路板層級元件充電模式靜電放電電流峰值，為了降低此電流峰值，以免損壞模組內的積體電路晶片，在放電路徑上可放置串聯電阻，實驗結果顯示此舉可大幅降低電路板層級元件充電模式靜電放電的電流峰值。第七章亦對數個以互補式金氧半製程製作的測試元件與測試電路進行晶片層級與電路板層級元件充電模式靜電放電測試，測試結果發現電路板層級元件充電模式靜電放電耐受度較低，且造成較嚴重的損壞情形，故電路板層級元件充電模式靜電放電對積體電路晶片的威脅比晶片層級元件充電模式靜電放電更為嚴重。 第八章總結本論文的研究成果，並提出數個接續本論文研究方向的研究題目。由於目前對電路板層級的靜電放電測試方式尚未有明確規範，本論文於附錄提出「積體電路之電路板層級元件充電模式靜電放電測試標準」提案，提案中詳細定義電路板層級靜電放電測試的各項測試條件與量測方式。 本論文所提出的各項新型設計，均搭配實驗晶片量測結果以驗證設計之理論，且有相對應的國際期刊與國際研討會論文發表。本論文中數個創新設計已提出專利申請。

With the continuous evolution of communication technology and integrated circuit (IC) process, wireless and wireline communication devices had become essential in daily life. By using the wireless communication devices to transmit data, users can access any information more conveniently. Advance wireline communication technology speedups the data transmission rate between the access points (AP) and the server. The continuous scaling of IC process technology further stimulates the demand for communication devices. All microelectronic products, including IC products, must meet the reliability specifications during mass production in order to be safely used and provide moderate life time. Electrostatic discharge (ESD), which has become one of the most important reliability issues in IC products, must be taken into consideration during the design phase of all IC products. Most of the failures and damages found in ICs were demonstrated to be related to ESD. To provide effective ESD protection for the IC, all pads which connect the IC and the external world need to be equipped with ESD protection circuits, including the input/output (I/O) pads, VDD pads, and VSS pads. However, the ESD protection devices at the I/O pads inevitably cause parasitic effects on the signal path. The radio-frequency (RF) front-end circuits in wireless communication devices need ESD protection design as well because they connect the RF transceiver to the external antenna or band-select filter. Since the RF front-end circuits operate in the frequency band ranging from several gigahertzes to tens of gigahertz, such a high operating frequency leads to strict limitations for the parasitic effects on the signal path. If the parasitic effects on the signal path are too large, RF circuit performance will be seriously degraded. Besides RF front-end circuits, the data rates of recent wireline communication standards also increase, so the parasitic effects on the signal paths of high-speed I/O interface circuits in wireline communication systems also need to be watched. The situation introduces the challenge in ESD protection design for RF circuits and high-speed I/O interface circuits, which is to achieve the highest ESD robustness with the smallest performance degradation. In other words, the parasitic effects of the ESD protection devices need to be minimized. Furthermore, the evolution of CMOS process increases the difficulty of ESD protection design. Advanced CMOS technologies not only increase the operating frequency of transistors but also reduce the noise of active devices and power consumption. With the continuous scaling of CMOS technology, the dimensions of CMOS devices are reduced, so more function blocks can be integrated into a single chip. This is the application of system on chip (SoC). However, ESD was not scaled down with the CMOS technology. MOS transistors fabricated in advanced CMOS processes have thinner gate oxide and thus lower gate-oxide breakdown voltage, so they are more vulnerable to ESD. Here comes the other design challenge, which is to reduce the voltage across the ESD protection devices under ESD stresses in advanced CMOS processes. The two aforementioned design challenges form the motivation of this dissertation. This dissertation begins at the design in the periphery of the IC, which is the bond pad, and enters the co-design of RF front-end and ESD protection circuits. Besides, this dissertation covers the whole-chip ESD protection design within a single chip and the investigation of board-level charged-device-model (CDM) ESD issue in IC products. The research topics including: (1) overview of previous works on ESD protection design for RF and high-speed I/O interface circuits, (2) ultra low-capacitance bond pad design, (3) ESD protection design for wideband distributed amplifier, (4) differential low-noise amplifier (LNA) with whole-chip ESD protection design, (5) ESD protection design for high-speed I/O interface circuits, and (6) investigation on board-level CDM ESD issue in IC products. In chapter 2, the published ESD protection designs for RF front-end circuits and high-speed interface circuits are overviewed. The designs are categorized with their individual advantages and disadvantages clearly analyzed. The RF performance degradation caused by ESD protection devices are illustrated with measured results. Besides, the characteristics of ESD protection devices under ESD stress conditions are quite important, because it determines the ESD robustness. The designs are categorized into three groups, which are the circuit solution, layout solution, and process solution. With the circuit technique, the impacts of parasitic effects caused by ESD protection devices on circuit performance can be significantly mitigated by impedance matching or impedance isolation. However, the increased chip area due to the extra components increases the fabrication cost. With the layout modification, the parasitic effects and dimensions of ESD protection devices can be moderately reduced. Since no extra component is used, the fabrication cost is lower than that with circuit technique. The third group is process modification. By modifying the doping concentration, the junction capacitance can be adjusted to reduce the parasitic effects of ESD protection devices. However, process modification is uncommon in general IC products. The design complexity, improved parasitic effect, ESD robustness, and area efficiency of all reported designs are compared in this chapter. Besides ESD protection devices, bond pads also cause impacts on circuit performance because of their parasitic capacitance. To mitigate the performance degradation, bond-pad capacitance needs to be minimized as well. A new low-capacitance bond pad structure in CMOS technology for RF applications is proposed in chapter 3. Three kinds of inductors stacked under the pad are used in the proposed bond pad structure. Experimental results in a 130-nm CMOS process have verified that the bond-pad capacitance is reduced due to the cancellation effect provided by the inductor embedded in the proposed bond pad structure. The bond-pad capacitance is reduced to almost 0 fF from 4.3 to 4.8 GHz. The proposed bond pad structure is fully compatible to general CMOS processes without any extra process modification. In chapter 4, two distributed ESD protection schemes are proposed and applied to protect distributed amplifiers against ESD stresses. Fabricated in a 0.25-μm CMOS process, the distributed amplifier with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V, while exhibits the flat-gain of 4.7 ± 1 dB from1 to 10 GHz. With the same total parasitic capacitance, the distributed amplifier with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level is over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 ± 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the wideband RF performances and high ESD robustness of the distributed amplifier can be successfully co-designed to meet the application specifications. Besides ESD protection design for wideband RF frond-end circuits, co-design of narrow band LNA and ESD protection circuit is proposed in chapter 5. A 5-GHz differential LNA is implemented in a 130-nm CMOS process, and several new ESD protection schemes are applied to this differential LNA. This is the first work which investigates the pin-to-pin ESD robustness of differential LNAs. All of the fabricated differential LNAs consume 10.3 mW from the 1.2-V power supply. The reference differential LNA without ESD protection has 16.2-dB power gain and 2.16-dB noise figure at 5 GHz. The conventional double-diode ESD protection scheme is realized for the differential LNA, which has 2.5-kV HBM and 200-V MM ESD robustness. The differential LNA with the double-diode ESD protection scheme has 17.9-dB power gain and 2.43-dB noise figure at 5 GHz. With the proposed double silicon-controlled rectifier (SCR) ESD protection scheme, the HBM and MM ESD levels are significantly improved to 6.5 kV and 500 V, respectively. Besides, the differential LNA with the double-SCR ESD protection has 17.9-dB power gain, and 2.54-dB noise figure at 5 GHz. Another proposed design uses an ESD bus between the differential input pads, which has 3-kV HBM and 100-V MM ESD robustness. The differential LNA with the proposed ESD bus has 18-dB power gain and 2.62-dB noise figure at 5 GHz. The ESD protection design using cross-coupled SCR devices between the differential input pads is also proposed. Besides providing ESD protection for a single input pad, pin-to-pin ESD protection is also achieved without adding any extra devices. This ESD protection scheme achieves 1.5-kV HBM and 150-V MM ESD levels, respectively. The power gain and noise figure of this differential LNA are 19.2 dB and 3.2 dB, respectively. By using other diodes beside the cross-coupled SCR devices, the turn-on efficiency of ESD protection devices can be enhanced. With the double diodes and the cross-coupled SCR devices, the ESD-protected differential LNA achieves 4-kV HBM and 300-V MM ESD robustness, and exhibits 19.1-dB power gain and 3-dB noise figure at 5 GHz. Chapter 6 presents the ESD protection design for high-speed I/O interface circuits. The ESD levels and parasitic capacitances of P+/N-well and N+/P-well ESD protection diodes with different dimensions are characterized in the beginning. Then the double-diode ESD protection scheme is applied to the dummy receiver NMOS and the dummy transmitter NMOS. Since the connection of the dummy receiver NMOS (dummy transmitter NMOS) is similar to that of the NMOS transistor in a receiver (transmitter) interface circuit, the ESD robustness of the dummy receiver NMOS (dummy transmitter NMOS) can be used to predict the ESD robustness of the high-speed interface circuit with this ESD protection scheme. This whole-chip ESD protection scheme is also applied to a 2.5-Gb/s high-speed I/O interface circuit, and the ESD robustness is larger than 3 kV in HBM with the parasitic capacitance of less than 250 fF. Moreover, a new ESD protection scheme is proposed in chapter 6. By replacing the N+/P-well diode between the input pad and VSS with the SCR, the ESD robustness can be further improved. In the ESD protection schemes in chapter 6, the ESD protection devices and part of the ESD detection circuit is placed under the I/O pad to reduce the chip area and the parasitic capacitance on the signal path. After finishing ESD protection design for a single chip, the chip needs to be installed in a module and module function test will be performed. At this time, board-level CDM ESD events may occur to damage the ICs. In chapter 7, the impacts caused by board-level CDM ESD events on IC products are investigated. The mechanism of board-level CDM ESD event is introduced first. Based on this mechanism, an experiment has been performed to investigate the board-level CDM ESD current waveforms under different sizes of printed circuit boards (PCBs), different charged voltages, and different series resistances in the discharging path. Experimental results have shown that the discharging current strongly depends on the PCB size, charged voltage, and series resistance. Moreover, chip-level and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes have been characterized and compared. Test results have shown that the board-level CDM ESD level of the test circuit is lower than the chip-level CDM ESD level, which demonstrates that the board-level CDM ESD event is more critical than the chip-level CDM ESD event. In addition, failure analysis reveals that the failure on the test circuit under the board-level CDM ESD test is much severer than that under the chip-level CDM ESD test. Chapter concludes the achievement in this dissertation, and suggests several future works in this field. Since the standard for the board-level CDM ESD test is not established so far, the proposal of the “Test standard for board-level charged-device-model electrostatic discharge robustness of integrated circuits” (in Chinese) is presented in the appendix. In the proposal, the test methodology and test conditions are clearly defined. In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of fabricated test chips have demonstrated the performance improvement. The achievements of this dissertation have been published in several international journal and conference papers. Several innovative designs have been applied for patents.