適應性多符號算術編碼之解碼器實現

Abstract

資料壓縮在通訊傳輸和資料儲存上扮演著一個相當重要的角色。而在資料壓縮中，算術編碼法的壓縮效能已可逼近理論上的熵值，因而備受注目。在應用上已經被廣泛的應用到工業界許多標準規格上。 傳統算術編碼對於不同的檔案作壓縮，壓縮效能就不一樣。基於此，本篇論文提出可參數化的有限歷史長度加權模型適應性算術編碼法。經由調整歷史緩衝區的大小和加權值的大小，我們決定六種不同的機率模組。對於不同的檔案，選擇最精確的機率模組以得到最佳的壓縮效能。並進一步把解碼部分的符號搜尋單元以位元比對二分搜尋法來實現以減少比對位元的次數而達到加速解碼器的目的。 最後將算術編解碼法中的解碼部分以TSMC 0.35um 1P4M COMS的製程來實現，其操作頻率高達71.4M Hz，採用100 LD CQFP 的封裝，晶片的面積為 2.86 x 2.86 。

Data compression played an important role in the data transmission and data storage. Arithmetic coding is an efficient loseless data compression technique and has been proposed in industrial standards. Traditionally, arithmetic coding applies certain specification for different types of data and results in average performance. To obtain the near-optimal performance, this thesis proposes a parameterized solution for adaptive arithmetic coding with a finite weighted history buffer. The thesis develops six probability models by tuning the size of history buffer and scaling weight. Our proposed decoder will employ one of the models for different files and allow users to set the selection of parameters. In addition to the parameterization, the thesis proposes a bit-wise binary searching algorithm to reduce the number of bit-compare operations. The reduction of operations can speed up our decoder significantly. As shown in the thesis, our decoder chip operates at 71.4 MHz clock rate and costs the area of 2.86*2.86 .