矽奈米尺寸金氧半場效電晶體的載子傳輸與重要元件參數之實驗性的研究

Abstract

本論文針對多閘極金氧半場效電晶體，比較其載子傳輸在重疊與非重疊閘源（汲）極結構中之差異，在具有重疊結構的元件中，我們觀察到次臨界電流特性依循波玆曼定律以及聲子為主要之載子碰撞特性，而在非具有重疊閘源（汲）極結構的元件中，我們發現次臨界區域與反轉區域之汲極電流對溫度並不敏感。我們的低溫量測結果指出，對於窄的重疊結構元件而言，載子在能階間碰撞是傳輸的主要機制，而對於非重疊結構元件而言，存在於非重疊區域的位能障會導致電導降低以及擾動。 此外，我們針對非具有重疊閘源（汲）極結構的多閘極金氧半場效電晶體，有系統地分析其可被控制的單電子效應與通道長、通道寬、閘極電壓、溫度之間的相依性。我們的研究指出，使用非重疊閘源（汲）極結構有助於實現單電子電晶體於金氧半場效電晶體，同時多閘極結構提供高閘極控制能力與高源（汲）極電阻的雙重優點，單電子效應被進一步地強化，目前的結果顯示，如果要實現室溫下可運作的單電子電晶體，除了元件尺寸必須要進一步維縮之外，穿隧位能障以及源（汲）極電阻必須要再進一步最佳化。由於單電子效應可被實現於最先進的金氧半場效電晶體，因此有助單電子電晶體整合於低功率互補式金氧半電路，以達到高密度的目的。 另外，我們評估從實驗中萃取通道背向散射的可行性、限制因素以及應用範圍，我們的研究指出，其困難點在於是否能正確決定低電場載子遷移率（μ0）、關鍵長度（l）與熱速度（υtherm）的溫度係數，透過我們所提出的自我相符萃取方法，我們不必預先假設：平均自由徑λ = (2kBTμ0/qυtherm)，l = kBT長，μ0 =低電場載子遷移率，以及非退化極限。用這個廣義溫度相依性的萃取方法來分析應力效應對通道背向散射的影響，我發現p型金氧半場效電晶體之通道背向散射會因單軸壓縮應力增強而下降。至於應力效應與靜電位能的相關性，第一次透過實驗方法萃取出。我們還進一步證實應力作用能夠透過增強彈道傳輸效率進而抑制汲極電流的變異。 還有，我們針對具有超薄氧化層的金氧半場效電晶體，研究其漏電流所引起異常電容電壓特性的問題，我們提出用本質輸入阻抗來模擬長通道金氧半場效電晶體之電容衰減，並反向重建應有的電容電壓特性，透過SPICE (Simulation Program with Integrated Circuit Emphasis)模擬，我們驗證本質輸入阻抗重建衰減電容的可靠度，而對於所重建的電容電壓特性，我們發現多晶矽閘極空乏效應可以被真實呈現，這個突破是有別於傳統使用頻率相依性所重建出的結果。由於重建方法的簡單性，因此適合作為大量製程觀察之用。

This thesis provides a comparative study of carrier transport characteristics for multiple-gate silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) with and without the non-overlapped gate to source/drain structure. For the overlapped devices, we observed the Boltzmann law in subthreshold characteristics and phonon-limited behavior in the inversion regime. For the non-overlapped devices, however, we found insensitive temperature dependence for drain current in both subthreshold and inversion regimes. Our low-temperature measurements indicate that the inter-subband scattering is the dominant carrier transport mechanism for narrow overlapped multiple-gate SOI MOSFETs (MuGFETs). For the non-overlapped MuGFETs, the voltage-controlled potential barriers in the non-overlapped regions are crucial and may give rise to the conductance reduction and fluctuation. Besides, we systematically present controlled single-electron effects in the non-overlapped MuGFETs with various gate length, fin width, gate bias and temperature. Our study indicates that using the non-overlapped gate to source/drain structure as an approach of the single-electron transistor (SET) in MOSFETs is promising. Combining the advantage of gate control and the constriction of high source/drain resistances, single-electron effects are further enhanced using the multiple-gate architecture. From the presented results, downsizing MuGFETs is needed for future room-temperature SET applications. Besides, the tunnel barriers and access resistances may need to be further optimized. Since single-electron effects can be achieved in state-of-the-art MOSFETs, it is beneficial to build SETs in low-power complementary metal-oxide-semiconductor (CMOS) circuits for the ultrahigh-density purpose. In addition, we have assessed the validity, limitation, and application of experimental channel backscattering extraction. Our study indicates that the difficulty of the temperature-dependent method lies in accurate determination of the temperature sensitivity of low-field mobility (μ0), critical length (l) and thermal velocity (υtherm). Through our proposed self-consistent approach, channel backscattering can be extracted without assuming λ = (2kBTμ0/qυtherm), l = kBT length, μ0 = low-field mobility, and the non-degenerate limit. Using the generalized temperature-dependent method, we have clarified that channel backscattering of nanoscale p-type MOSFETs can be reduced by the uniaxially compressive strain. Moreover, we have experimentally extracted the electrostatic potential of the source-channel junction barrier with accurate strain and gate voltage dependence. We have demonstrated that the strain technology can improve the drain current variation as well as the mismatch properties through the enhanced ballistic efficiency. Moreover, we have investigated anomalous inversion capacitance-voltage (C−V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C−V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (Rii). The concept of Rii has been validated by segmented SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. Our reconstructed C−V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method, and agree well with the NCSU CVC (C−V analysis software developed by the North Carolina State University) simulation results. Due to its simplicity, our proposed Rii approach may provide an option for regular process monitoring purposes.