前瞻非揮發性奈米晶體記憶體元件之製作與特性研究

Abstract

本論文主要是針對非揮發性奈米點記憶體元件做研究。我們成功的製作出用鈷作為奈米點的結構。鈷奈米點包含在以二氧化矽以及二氧化鉿分別當作穿遂氧化層和控制氧化層之間。通過電性分析，可以發現其具有明顯的記憶效應。在5伏特的低操作電壓下，其記憶窗口(memory window)約為1伏特左右。同時，其保存特性(retention characteristic)也相當驚人。而且，其忍耐度(endurance)在經過106次的寫入/抹除之後，也沒有衰退。 同時，我們也成功製作出以鎳奈米點當作分離式電荷儲存點記憶體，埋在二氧化矽以及二氧化鉿之間的結構。由穿遂式顯微鏡得知，鎳奈米點平均大小約為5奈米以及密度約為3.9□1012/cm2。鎳奈米點記憶體，在4伏特的寫入電壓操作下，有1伏特的切入電壓偏移(threshold voltage shift)。鎳奈米點記憶體具有很長的保存時間(retention time)，極少的電荷流失率(charge loss rate)。此外，記憶體的忍耐度即使到達106次的寫入/抹除之後，也不會衰退的現象出現。 此外，我們也成功的製作以矽化鈷當作奈米點的記憶體。矽化鈷奈米點，埋在分別以二氧化矽以及二氧化鉿為穿遂氧化層和控制氧化層之間。其中我們以電子繞射圖樣分析(electron diffraction pattern)，確定奈米點為矽化鈷。矽化鈷奈米點記憶體，在9伏特的電壓操作下有約為1.6伏特的切入電壓偏移。具有很長時間的保存時間且很低的電荷流失率。忍耐度即使到達106次的寫入/抹除之後也沒有變差。 同時，我們也成功製作出以矽化鎳奈米點在二氧化矽以及二氧化鉿之間的結構。在電性方面的特性可以發現有很大的記憶窗口。在操作電壓為4伏特的低電壓下，很明顯的得知有1.3伏特切入電壓偏移。這種的結構的製程將與現今半導體業界的製程相符合。 最後，在論文中我們成功的製作出多層奈米點結構的記憶體。這種多層奈米點的記憶體的優點將提高記憶體的效應。藉著增加奈米點的密度可增進保存時間的特性。雙層的奈米點記憶體比起單層的記憶體有更多的電子儲存在裡面。雙層的矽化鈷奈米點記憶體比單層的記憶體有更好的保存特性。然而，雙層結構的記憶體之所以有較佳的保存特性是因為在上層的Coulomb-blockage 效應，使得底層的電子不易流失。所以，藉由雙層的奈米點可以有效增進奈米點記憶體的記憶效應。

We have studied experimentally and theoretically nonvolatile nanocrystal memory devices. On the study of nanocrystal memory, the Co nanocrystals using SiO2 and HfO2 as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5V, the memory window was estimated to ~ 1V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 106 write/erase cycles. A distributed charge storage with Ni nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated in this study. The mean size and aerial density of the Ni nanocrystals are estimated to be about 5 nm and 3.9□1012/cm2, respectively. The nonvolatile memory device with Ni nanocrystals exhibits 1 V threshold voltage shift under 4 V write operation. The device has a long retention time with a small charge lose rate. Besides, the endurance of the memory device is not degraded up to 106 write/erase cycles. On the study of the CoSi nanocrystals with distributed charge storage elements embedded between the SiO2 and HfO2 layer has been proposed. The nanocrystals were identified to be CoSi phase by the analysis of electron diffraction pattern. The nonvolatile memory device with CoSi nanocrystals exhibits 1.6 V threshold voltage shift under 9 V write operation. The device has a long retention time with a small charge lose rate. In addition, the endurance is not degraded up to 106 write/erase cycles. Also, a nonvolatile memory device with NiSi2 nanocrystals embedded in the SiO2 and HfO2 layer has been fabricated. A significant memory effect is observed on the characterization of the electrical properties. When a low operating voltage, 4V, is applied, a significant threshold-voltage shift of 1.3V, is observed. The processing of this structure is compatible with the current manufacturing technology of semiconductor industry. Finally, the nonvolatile memory device with multilayer nanocrystals has advantages such as the memory effects can be increased by the increasing density of the nanocrystals and the whole retention characteristic can be improved. There are much more electrons that can be stored in the double layer than single layer nanocrystal memory device. The double layer CoSi2 nanocrystals have better retention characteristic than the single layer. The good retention characteristic of the double layer device is due to the Coulomb-blockage effects on the top layer nanocrystals from the bottom layer nanocrystals. So, the memory effects of the nonvolatile memory device can be improved by using the double layer nanocrystals.