一個應用於32~96KHz SPDIF/AES訊號之時脈回復器電路的設計

Abstract

在通訊系統中，由於訊號經過長通道的傳送，受到許多雜訊的干擾而帶有大量的抖動，因此在接收端我們需要一個時脈回復器的電路來還原出一個低抖動的時脈以正確的取樣資料。根據不同的輸入訊號規格有不同的時脈回復器電路的設計考量。在處理32~96KHz取樣頻率的音頻輸入訊號時，它的困難處在於輸入訊號的頻率範圍很廣，傳統的時脈資料回復器架構在處理這樣的寬頻率範圍訊號有其困難點，因此我們提出一種新的時脈資料回復器架構來還原時脈。我們的設計是以雙迴路以鎖相迴路為基礎的時脈資料回復器電路為基本架構，所使用的頻率偵測器則為一個對SPDIF/AES訊號擁有無限寬鎖定範圍的頻率偵測器，同時我們修改其電路以解決此頻率偵測器在一開始壓控振盪器還未起振時無法正確操作的問題。為了避免此頻率偵測器在頻率鎖定的狀況下還持續的干擾迴路，我們設計一個能針對不同輸入頻率且易實現的頻率鎖定偵測器用來切換相位和頻率偵測雙迴路。模擬結果顯示系統的鎖定時間小於5ms，峰對峰的週期抖動為1ns，而均方根週期抖動則為191.17ps。

In communication systems, the received signals are usually contaminated by the channel noise and distorted by the finite channel bandwidth. As a result, they often carry a lot of jitter. At the receiver end, we need a clock recovery circuit to recovery a low jitter clock and use the recovered clock to sample the input data. For popular audio applications, the specification of the input clock is in the range of 32~96 KHz. Traditional clock recovery circuits are not suitable for recovering the clock of such a wide frequency range signal. This thesis proposes a new clock recovery circuit to address the issue. Our design is based on a dual-loop, PLL based, clock recovery architecture with a modified wide locking range frequency detector. We also proposed a modified frequency detector to address the possible dead-lock scenario. To avoid the frequency detector subsequently disturbing the control voltage of the voltage control oscillator, a simple frequency lock-indicator purely implemented by digital circuits has been added. It turns off the frequency locked loop when the frequency is locked. Our frequency lock-indicator doesn’t require any extra reference clock and is capable of indicating when the frequency is locked even if the clock of the input signal is not fixed. The simulation results showed that the lock-in time is under 5ms, the peak-to peak period jitter is 1ns, and the rms period jitter is 191.17ps.