一個操作在1.25Gb/s具備降低抖動能力的突發式時脈回復電路

Abstract

一具備降低抖動功能的突發式時脈及資料回復電路被實現在本研究，並將其應用於被動光纖網路系統。此電路使用了半速率架構並操作在1.25-Gb/s。在此時脈及資料回復電路中，我們在邊緣偵測器裡使用了一個半位元時間延遲產生電路來改善抖動的累積：此乃藉由一個具備多組延遲時間值的延遲時間產生電路來產生；並利用動態平均的概念來產生半位元的時間延遲以造成最小的抖動產生。本晶片使用0.18 mm互補式金氧半製程來製造，量測到的回復時脈訊號在抖動降低技術未啟動時的峰對峰抖動值為130ps；在抖動降低技術啟動後的峰對峰抖動值為114.3ps，改善了13.7%。當操作電壓為1.8V之下，整個時脈與資料回復電路的功率消耗為36mW。晶片面積為0.99 × 0.97mm2。

A 1.25-Gb/s half rate Burst-Mode clock and data recovery (BMCDR) circuit with jitter reduction technique for PON application is presented in this thesis. There are several delays in the half of bit time (Tbit/2) delay generating circuit of the edge detector to create a delay time that falls exactly on half of bit time (Tbit/2) delay to minimize jitter generation. The measured peak to peak recovered clock jitter when the jitter reduction technique is disable is 130ps; while the jitter reduction technique is active, the measured peak to peak clock jitter is 114.3ps, reduced by 13.7%. The chip was fabricated with TSMC 0.18 □m CMOS technology. The die area of the CDR is 0.99 × 0.97 mm2, and power consumption is 36mW under a 1.8-V supply voltage.