一個適用於多頻帶快速鎖定的突發式時脈與資料回復電路

Abstract

積體電路技術的快速進步早已經鞭策著低價又便宜的寬頻存取服務的發展，對於發展經濟型高速的光纖用戶網路來說，以被動光纖網路為基礎的光纖到家系統被認為是前景一片看好的。在被動光纖網路中，時脈與資料回復電路(CDR)在收發機裡扮演一個非常重要的角色，且此種收發機可以應用在許多的通訊系統裡，比如光纖通訊和平面顯示器介面等。因此，在此應用中，如何實現一個具有快速鎖定的脈衝式時脈與資料回復電路是一個關鍵性的課題。此外，如何利用較便宜的互補式金屬氧化半導體製程來實現高速的時脈與資料回復電路將是可以用相對較低的成本而達到更高傳輸頻寬的不二法門。 在通訊系統中，通常接收端接受到的資料都是非同步的，並且受到了雜訊干擾使得資料失真，所以在接收端中的時脈與資料回復電路必須從資料中萃取出時脈的資訊，並利用此資訊將輸入的資料作重新萃取的動作，以便減少錯誤率。除此之外，為了使傳輸的效益更大，在Gigabit PON (GPON)的系統中要求CDR能夠快速的鎖定，而由於本設計的時脈與資料回復電路主要達到快速鎖定為目的，因此快速鎖定為本晶片設計的重點之一。 本電路設計主要實現一個閘式壓控振盪器為基準的突發式時脈與資料回復電路，利用數位鎖頻迴路去鎖定閘式壓控振盪器頻率，再交給閘式壓控振盪器電路進行快速相位的重置，和資料與相位的鎖定，此電路所提出的閘式壓控振盪器採1/7速率的操作，也就是在一個時脈週期之內有七筆傳送資料，進而達到高速操作及低功率消耗之目的，且利用多模數的除頻器使此電路可以應用在不同頻帶，資料傳送方式為序列資料輸入晶片解多工成七筆並列資料輸出，此電路採用TSMC-90nm CMOS製程技術，操作電壓為1.2V，總面積為1.162 x 1.205mm2，當資料頻率為622.16Mbps、1244 Mbps、2488 Mbps、4977 Mbps和7Gbps時，總功率消耗分別為1.5毫瓦、3毫瓦、6毫瓦、12毫瓦和17毫瓦。

The rapid progress in integrated circuit (IC) techniques has spurred the development of low-cost and convenient broadband access services. Fiber-to-the-home (FTTH) system based on passive optical network (PON) is considered as a promising technology for deploying economically high-speed subscriber networks. In the passive optical network, clock and data recovery (CDR) circuit plays an important role in the transceiver. The application of the communication system such as passive optical network (PON) and FPD-Link suits this transceiver. Thus, how to realize a burst-mode CDR with rapid lock time is a critical issue in this application. Besides, implementing the high speed CDR in an inexpensive CMOS technology is the key to enable higher bandwidth communications at a relatively lower cost. For communications, the data at the receiver is usually asynchronous, and it suffered distortion by noise and jitter. A clock and data recovery circuit at the receiver senses the data and produces a periodic clock, and retimes the input data by using the produced periodic clock to reduce the bit error rate. For higher efficiency of transmission, Gigabit PON specifications have only constraints on lock time, and this design exhibits instantaneous response. A gated voltage-controlled oscillator based burst mode clock and data recovery circuit is presented. The frequency of gated voltage-controlled oscillator is locked by using the digitally assisted frequency locked loop, and then the gated voltage-controlled oscillator takes over to achieve instantaneous phase re-align and the received data with clock synchronization. The 1/7-rate gated voltage-controlled oscillator is presented. There are seven transmitted data within a periodic clock in order to achieve high speed operation and low power consumption. It can cover multi-band by using the truly modulus programmable divider, and the type of the data transmission is serial in parallel out. Implemented in a 90nm CMOS technology, the area is 1.162x1.205 mm2 including PAD, The chip consumes 1.5 mW, 3 mW, 6 mW, 12 mW and 17 mW when the data rate are 622.16Mbps, 1244Mbps, 2488Mbps, 4977Mbps and 7Gbps from 1.2V supply.