A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter Suppression

Abstract

A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1: 5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI(pp) input data jitter, the recovered clock jitter at 2GHz is 2.94ps(rms). The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200x150 mu m(2).