標題: 三相無刷直流馬達之無感測器驅動技術研究
The Research of The Sensorless Drive Technology for The Three-Phase Brushless DC Motor
作者: 賴威勳
Wei-hsun Lai
林錫寬
Shir-Kuan Lin
電控工程研究所
關鍵字: 無感測;無刷直流;驅動;sensorless;DC;brushless;three-phase
公開日期: 2004
摘要: 由於無刷直流馬達無感測器驅動技術具有高轉速、響應快以及小型化、薄型化的優點,所以已經被廣泛地使用在硬碟機、光碟機等資訊商品上。然而因為沒有在馬達上安裝位置感測器,所以需要無感測驅動技術偵測馬達轉子位置以達到換相控制。大部分的無感測換相控制技術會利用馬達旋轉時產生的反電動勢,但是在利用反電動勢做位置 偵測時都會面臨到一個共同的難題:反電動勢的振幅是與轉速成正比,所以在低轉速時振幅太小,容易受到雜訊干擾,若此時以閉迴路換相控制技術驅動馬達,則在進行反電動勢零交越點判斷時,會因振幅太小而偵測不到或是因雜訊而判斷錯誤的情況發生,導致錯誤換相的動作,因此需要開迴路啟動程序先提升馬達轉速,當有足夠大的反電動勢之後,便可以切換到閉迴路程序,以反電動勢進行換相控制。因此,在開迴路啟動程序中最重要的就是如何在愈短時間內讓反電動勢振幅愈高,便可以愈早切換到閉迴路程序,本論文在此提出兩個新型開迴路序列,能夠在短時間內增大反電動勢振幅,所以能比傳統式開迴路換相序列更早切換至閉迴路程序,縮短馬達暫態響應的時間。 本論文選擇以無感測驅動IC:BD6609fv驅動一顆三相無刷直流馬達,並提出實驗方法以測試IC內部的無感測驅動技術,希望透過此顆IC的實作能獲得市面上比較成熟的無感測驅動技術。另外為了驗證無感測驅動技術,本論文以Visual C++ 架構一個模擬系統,透過這個模擬系統,我們可以模擬出各個開迴路換相序列的優缺點。而為了與模擬互相驗證,本論文藉由一套以Nios發展板中之FPGA為控制核心及馬達週邊相關電路的實驗平台,實現開迴路換相序列的實作驗證。
Sensorless brushless DC motors have been widely used for HDD ,DVD devices because of their high speed, fast response and small size. However, the rotation of motor requires special techniques because there are not any position sensors in the motor. Most techniques use the back EMF to detect motor position. However, the above techniques have a common problem: The amplitude of back EMF is too small at low speed to be detected because the amplitude is proportional to rotation speed. Therefore we need a serise of open-loop sequence to accelerate the motor speed. When the back EMF is large enough, the mode is changed from open-loop mode to close-loop mode and the motor is self-commutated by the back EMF. Thus the important thing during open-loop mode is to acquire the largest amplitude of back EMF as quickly as possible.This paper raises two new open-loop sequences that could acquire larger amplitude of back EMF in the short time. Therefore the time of the start-up of the motor can be shortened. Besides, in order to make research of the sensorless drive techniques of sensorless contorl IC, his paper uses IC:BD6609fv to drive a BLDCM and proposes many method to test this IC. The proposed new open-loop sequences are verified with the Visual C++ simulation firstly and then is realized with FPGA-based chip collocating with voltage sensing circuit, motor drive and peripheral circuit for proving the announced sequences are valid .
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009212538
http://hdl.handle.net/11536/68323
Appears in Collections:Thesis


Files in This Item:

  1. 253801.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.