以平台架構為基礎之JPEG2000影像編碼矽智產設計

Abstract

JPEG2000影像壓縮技術可以提供我們高畫質，高解析度，高壓縮倍率的影像；但是相對地，其演算法比其他的靜態影像壓縮法複雜得多。所以將JPEG2000的演算法用硬體實現有其必要性和實用性。 JPEG2000其中一項重要的特色就是精確的壓縮位元率控制，但是複雜的演算法不太適合硬體實作。本論文提出一個位元率控制的方法，非常適合實現在硬體上。此架構並且適用於傳統的DWT與本實驗室自行開發的QCB-Based DWT中。 在SoC (System-on-a-Chip)的時代來臨之後，TTM (Time-To-Market)的觀念越來越為人所重視；為了解決這個問題，設計可以Reusable的IP (Intellectual Property)就變得格外重要，尤其矽智財又牽涉到SoC的實現，因此IP-Based Design便孕育而生。但更進一步的，如何快速且有效率的整合這些IPs，Platform-Based Design才是重要關鍵。 本論文最後將JPEG2000實現成IP的形式，使用者可以依照自己的需求，參數化該IP，該IP產生器便會產生出符合使用者規格的JPEG2000編碼器包含RTL code、testbench、synthesis scrip等；除此之外，也一併提供了包括ASIC和FPGA兩種設計流程中整套tool chain所有的script files，增進設計自動化且縮短了整個設計的時程。

JPEG2000 image compression technology can provide higher quality, higher resolution and higher compression ratio of an image. But JPEG2000 algorithm is more complex than the other still image compression relatively. It is necessary and usable to develop JPEG2000 with the hardware realization. One of the important features of JPEG2000 is the accurate rate-control scheme but it is not suitable for hardware design. A rate-control scheme which is easy for hardware implementation is proposed in this thesis. The architecture is suitable for the traditional DWT and QCB-based DWT. The coming of SoC (System-on-a-Chip) era has been urging the emphasis of the people towards the TTM (Time-To-Market) concept. To solve this problem, design of reusable IP (Intellectual Property) is more important. Especially IP is concern with realization of SoC. That is why IP-based design was appeared. Furthermore, the platform-based design is the key that how to integrate these IPs rapidly and efficiently. Finally, we design JEPG2000 not only an IC but also an IP. Users can configure this IP with their requirements, and the JPEG2000 ModelGen will generate the RTL code, testbench and synthesis scrip user-defined. Moreover, the ModelGen also generates all script files of tools which in ASIC and FPGA design flow. It can decrease the development time and increase design automation.