標題: A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs
作者: Guo, Jyh-Chyurn
Yeh, Chih-Ting
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: MOSFET;nanoscale;parasitic capacitance;3-D capacitor model
公開日期: 1-Aug-2009
摘要: A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance C(of) dominates around 25% of the intrinsic gate capacitance (C(gint)) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C(of)/C(gint) above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.
URI: http://dx.doi.org/10.1109/TED.2009.2022679
http://hdl.handle.net/11536/6847
ISSN: 0018-9383
DOI: 10.1109/TED.2009.2022679
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 56
Issue: 8
起始頁: 1598
結束頁: 1607
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